*** empty log message ***

[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index 7c27f11127ac18696373f59f29723893ee236acc..2fa86dfa9f3b846d557ddf7b9467cf80cf7893dd 100644 (file)
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -47,6 +47,8 @@ enum gdb_regnum {
   ARM_WCGR0_REGNUM,            /* WMMX general purpose registers.  */
   ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
   ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
+  ARM_D0_REGNUM,               /* VFP double-precision registers.  */
+  ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
 
   ARM_NUM_REGS,
 
@@ -151,6 +153,13 @@ struct gdbarch_tdep
   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 
   int have_fpa_registers;      /* Does the target report the FPA registers?  */
+  int have_vfp_registers;      /* Does the target report the VFP registers?  */
+  int have_vfp_pseudos;                /* Are we synthesizing the single precision
+                                  VFP registers?  */
+  int have_neon_pseudos;       /* Are we synthesizing the quad precision
+                                  NEON registers?  Requires
+                                  have_vfp_pseudos.  */
+  int have_neon;               /* Do we have a NEON unit?  */
 
   CORE_ADDR lowest_pc;         /* Lowest address at which instructions 
                                   will appear.  */
@@ -170,13 +179,120 @@ struct gdbarch_tdep
 
   /* Cached core file helpers.  */
   struct regset *gregset, *fpregset;
+
+  /* ISA-specific data types.  */
+  struct type *arm_ext_type;
+  struct type *neon_double_type;
+  struct type *neon_quad_type;
+};
+
+/* Structures used for displaced stepping.  */
+
+/* The maximum number of temporaries available for displaced instructions.  */
+#define DISPLACED_TEMPS                        16
+/* The maximum number of modified instructions generated for one single-stepped
+   instruction, including the breakpoint (usually at the end of the instruction
+   sequence) and any scratch words, etc.  */
+#define DISPLACED_MODIFIED_INSNS       8
+
+struct displaced_step_closure
+{
+  ULONGEST tmp[DISPLACED_TEMPS];
+  int rd;
+  int wrote_to_pc;
+  union
+  {
+    struct
+    {
+      int xfersize;
+      int rn;                     /* Writeback register.  */
+      unsigned int immed : 1;      /* Offset is immediate.  */
+      unsigned int writeback : 1;  /* Perform base-register writeback.  */
+      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
+    } ldst;
+
+    struct
+    {
+      unsigned long dest;
+      unsigned int link : 1;
+      unsigned int exchange : 1;
+      unsigned int cond : 4;
+    } branch;
+
+    struct
+    {
+      unsigned int regmask;
+      int rn;
+      CORE_ADDR xfer_addr;
+      unsigned int load : 1;
+      unsigned int user : 1;
+      unsigned int increment : 1;
+      unsigned int before : 1;
+      unsigned int writeback : 1;
+      unsigned int cond : 4;
+    } block;
+
+    struct
+    {
+      unsigned int immed : 1;
+    } preload;
+
+    struct
+    {
+      /* If non-NULL, override generic SVC handling (e.g. for a particular
+         OS).  */
+      int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
+                         struct regcache *regs,
+                         struct displaced_step_closure *dsc);
+    } svc;
+  } u;
+  unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
+  int numinsns;
+  CORE_ADDR insn_addr;
+  CORE_ADDR scratch_base;
+  void (*cleanup) (struct gdbarch *, struct regcache *,
+                  struct displaced_step_closure *);
 };
 
+/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
+   write may write to the PC, specifies the way the CPSR T bit, etc. is
+   modified by the instruction.  */
+
+enum pc_write_style
+{
+  BRANCH_WRITE_PC,
+  BX_WRITE_PC,
+  LOAD_WRITE_PC,
+  ALU_WRITE_PC,
+  CANNOT_WRITE_PC
+};
+
+extern void
+  arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn,
+                             CORE_ADDR from, CORE_ADDR to,
+                             struct regcache *regs,
+                             struct displaced_step_closure *dsc);
+extern void
+  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
+                             CORE_ADDR to, struct displaced_step_closure *dsc);
+extern ULONGEST
+  displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno);
+extern void
+  displaced_write_reg (struct regcache *regs,
+                      struct displaced_step_closure *dsc, int regno,
+                      ULONGEST val, enum pc_write_style write_pc);
 
 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
 int arm_software_single_step (struct frame_info *);
 
+extern struct displaced_step_closure *
+  arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
+                               struct regcache *);
+extern void arm_displaced_step_fixup (struct gdbarch *,
+                                     struct displaced_step_closure *,
+                                     CORE_ADDR, CORE_ADDR, struct regcache *);
+
 /* Functions exported from armbsd-tdep.h.  */
 
 /* Return the appropriate register set for the core section identified