/* Common target dependent code for GDB on ARM systems.
- Copyright (C) 2002, 2003, 2007, 2008, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2002-2015 Free Software Foundation, Inc.
This file is part of GDB.
/* Forward declarations. */
struct gdbarch;
struct regset;
+struct address_space;
-/* Register numbers of various important registers. */
-
-enum gdb_regnum {
- ARM_A1_REGNUM = 0, /* first integer-like argument */
- ARM_A4_REGNUM = 3, /* last integer-like argument */
- ARM_AP_REGNUM = 11,
- ARM_IP_REGNUM = 12,
- ARM_SP_REGNUM = 13, /* Contains address of top of stack */
- ARM_LR_REGNUM = 14, /* address to return to from a function call */
- ARM_PC_REGNUM = 15, /* Contains program counter */
- ARM_F0_REGNUM = 16, /* first floating point register */
- ARM_F3_REGNUM = 19, /* last floating point argument register */
- ARM_F7_REGNUM = 23, /* last floating point register */
- ARM_FPS_REGNUM = 24, /* floating point status register */
- ARM_PS_REGNUM = 25, /* Contains processor status */
- ARM_WR0_REGNUM, /* WMMX data registers. */
- ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
- ARM_WC0_REGNUM, /* WMMX control registers. */
- ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
- ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
- ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
- ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
- ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
- ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
- ARM_D0_REGNUM, /* VFP double-precision registers. */
- ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
-
- ARM_NUM_REGS,
-
- /* Other useful registers. */
- ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
- THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
- ARM_NUM_ARG_REGS = 4,
- ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
- ARM_NUM_FP_ARG_REGS = 4,
- ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
-};
+#include "arch/arm.h"
/* Size of integer registers. */
#define INT_REGISTER_SIZE 4
bits. DWORD aligned they use 96 bits. */
#define FP_REGISTER_SIZE 12
+/* Say how long VFP double precision registers are. Used for documentation
+ purposes and code readability. These are fixed at 64 bits. */
+#define VFP_REGISTER_SIZE 8
+
/* Number of machine registers. The only define actually required
is gdbarch_num_regs. The other definitions are used for documentation
purposes and code readability. */
#define CPSR_T 0x20
+#define XPSR_T 0x01000000
+
/* Type of floating-point code in use by inferior. There are really 3 models
that are traditionally supported (plus the endianness issue), but gcc can
only generate 2 of those. The third is APCS_FLOAT, where arguments to
enum arm_float_model fp_model; /* Floating point calling conventions. */
int have_fpa_registers; /* Does the target report the FPA registers? */
- int have_vfp_registers; /* Does the target report the VFP registers? */
+ int have_wmmx_registers; /* Does the target report the WMMX registers? */
+ /* The number of VFP registers reported by the target. It is zero
+ if VFP registers are not supported. */
+ int vfp_register_count;
int have_vfp_pseudos; /* Are we synthesizing the single precision
VFP registers? */
int have_neon_pseudos; /* Are we synthesizing the quad precision
have_vfp_pseudos. */
int have_neon; /* Do we have a NEON unit? */
+ int is_m; /* Does the target follow the "M" profile. */
CORE_ADDR lowest_pc; /* Lowest address at which instructions
will appear. */
- const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
+ const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
int arm_breakpoint_size; /* And its size. */
- const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn. */
+ const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */
int thumb_breakpoint_size; /* And its size. */
- int jb_pc; /* Offset to PC value in jump buffer.
+ /* If the Thumb breakpoint is an undefined instruction (which is
+ affected by IT blocks) rather than a BKPT instruction (which is
+ not), then we need a 32-bit Thumb breakpoint to preserve the
+ instruction count in IT blocks. */
+ const gdb_byte *thumb2_breakpoint;
+ int thumb2_breakpoint_size;
+
+ int jb_pc; /* Offset to PC value in jump buffer.
If this is negative, longjmp support
will be disabled. */
size_t jb_elt_size; /* And the size of each entry in the buf. */
/* Convention for returning structures. */
enum struct_return struct_return;
- /* Cached core file helpers. */
- struct regset *gregset, *fpregset;
-
/* ISA-specific data types. */
struct type *arm_ext_type;
struct type *neon_double_type;
struct type *neon_quad_type;
+
+ /* Return the expected next PC if FRAME is stopped at a syscall
+ instruction. */
+ CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
+
+ /* syscall record. */
+ int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};
/* Structures used for displaced stepping. */
{
/* If non-NULL, override generic SVC handling (e.g. for a particular
OS). */
- int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
- struct regcache *regs,
+ int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
struct displaced_step_closure *dsc);
} svc;
} u;
+
+ /* The size of original instruction, 2 or 4. */
+ unsigned int insn_size;
+ /* True if the original insn (and thus all replacement insns) are Thumb
+ instead of ARM. */
+ unsigned int is_thumb;
+
+ /* The slots in the array is used in this way below,
+ - ARM instruction occupies one slot,
+ - Thumb 16 bit instruction occupies one slot,
+ - Thumb 32-bit instruction occupies *two* slots, one part for each. */
unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
int numinsns;
CORE_ADDR insn_addr;
};
extern void
- arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn,
- CORE_ADDR from, CORE_ADDR to,
- struct regcache *regs,
+ arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
+ CORE_ADDR to, struct regcache *regs,
struct displaced_step_closure *dsc);
extern void
arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
CORE_ADDR to, struct displaced_step_closure *dsc);
extern ULONGEST
- displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno);
+ displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
+ int regno);
extern void
displaced_write_reg (struct regcache *regs,
struct displaced_step_closure *dsc, int regno,
CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
+void arm_insert_single_step_breakpoint (struct gdbarch *,
+ struct address_space *, CORE_ADDR);
+int arm_deal_with_atomic_sequence (struct frame_info *);
int arm_software_single_step (struct frame_info *);
+int arm_frame_is_thumb (struct frame_info *frame);
extern struct displaced_step_closure *
arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
struct displaced_step_closure *,
CORE_ADDR, CORE_ADDR, struct regcache *);
+/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
+extern int arm_psr_thumb_bit (struct gdbarch *);
+
+/* Is the instruction at the given memory address a Thumb or ARM
+ instruction? */
+extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
+
+extern int arm_process_record (struct gdbarch *gdbarch,
+ struct regcache *regcache, CORE_ADDR addr);
/* Functions exported from armbsd-tdep.h. */
/* Return the appropriate register set for the core section identified
by SECT_NAME and SECT_SIZE. */
-extern const struct regset *
- armbsd_regset_from_core_section (struct gdbarch *gdbarch,
- const char *sect_name, size_t sect_size);
+extern void
+ armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
+ iterate_over_regset_sections_cb *cb,
+ void *cb_data,
+ const struct regcache *regcache);
+
+/* Target descriptions. */
+extern struct target_desc *tdesc_arm_with_m;
+extern struct target_desc *tdesc_arm_with_iwmmxt;
+extern struct target_desc *tdesc_arm_with_vfpv2;
+extern struct target_desc *tdesc_arm_with_vfpv3;
+extern struct target_desc *tdesc_arm_with_neon;
#endif /* arm-tdep.h */