/* Common target dependent code for GDB on ARM systems.
- Copyright 2002 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc.
This file is part of GDB.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/* Register numbers of various important registers. Note that some of
- these values are "real" register numbers, and correspond to the
- general registers of the machine, and some are "phony" register
- numbers which are too large to be actual register numbers as far as
- the user is concerned but do serve to get the desired values when
- passed to read_register. */
-
-#define ARM_A1_REGNUM 0 /* first integer-like argument */
-#define ARM_A4_REGNUM 3 /* last integer-like argument */
-#define ARM_AP_REGNUM 11
-#define ARM_SP_REGNUM 13 /* Contains address of top of stack */
-#define ARM_LR_REGNUM 14 /* address to return to from a function call */
-#define ARM_PC_REGNUM 15 /* Contains program counter */
-#define ARM_F0_REGNUM 16 /* first floating point register */
-#define ARM_F3_REGNUM 19 /* last floating point argument register */
-#define ARM_F7_REGNUM 23 /* last floating point register */
-#define ARM_FPS_REGNUM 24 /* floating point status register */
-#define ARM_PS_REGNUM 25 /* Contains processor status */
-
-#define ARM_FP_REGNUM 11 /* Frame register in ARM code, if used. */
-#define THUMB_FP_REGNUM 7 /* Frame register in Thumb code, if used. */
-
-#define ARM_NUM_ARG_REGS 4
-#define ARM_LAST_ARG_REGNUM ARM_A4_REGNUM
-#define ARM_NUM_FP_ARG_REGS 4
-#define ARM_LAST_FP_ARG_REGNUM ARM_F3_REGNUM
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#ifndef ARM_TDEP_H
+#define ARM_TDEP_H
+
+/* Forward declarations. */
+struct gdbarch;
+struct regset;
+
+/* Register numbers of various important registers. */
+
+enum gdb_regnum {
+ ARM_A1_REGNUM = 0, /* first integer-like argument */
+ ARM_A4_REGNUM = 3, /* last integer-like argument */
+ ARM_AP_REGNUM = 11,
+ ARM_SP_REGNUM = 13, /* Contains address of top of stack */
+ ARM_LR_REGNUM = 14, /* address to return to from a function call */
+ ARM_PC_REGNUM = 15, /* Contains program counter */
+ ARM_F0_REGNUM = 16, /* first floating point register */
+ ARM_F3_REGNUM = 19, /* last floating point argument register */
+ ARM_F7_REGNUM = 23, /* last floating point register */
+ ARM_FPS_REGNUM = 24, /* floating point status register */
+ ARM_PS_REGNUM = 25, /* Contains processor status */
+ ARM_WR0_REGNUM, /* WMMX data registers. */
+ ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
+ ARM_WC0_REGNUM, /* WMMX control registers. */
+ ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
+ ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
+ ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
+ ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
+ ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
+ ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
+
+ ARM_NUM_REGS,
+
+ /* Other useful registers. */
+ ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
+ THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
+ ARM_NUM_ARG_REGS = 4,
+ ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
+ ARM_NUM_FP_ARG_REGS = 4,
+ ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
+};
/* Size of integer registers. */
-#define INT_REGISTER_RAW_SIZE 4
-#define INT_REGISTER_VIRTUAL_SIZE 4
+#define INT_REGISTER_SIZE 4
/* Say how long FP registers are. Used for documentation purposes and
code readability in this header. IEEE extended doubles are 80
bits. DWORD aligned they use 96 bits. */
-#define FP_REGISTER_RAW_SIZE 12
-
-/* GCC doesn't support long doubles (extended IEEE values). The FP
- register virtual size is therefore 64 bits. Used for documentation
- purposes and code readability in this header. */
-#define FP_REGISTER_VIRTUAL_SIZE 8
+#define FP_REGISTER_SIZE 12
/* Status registers are the same size as general purpose registers.
Used for documentation purposes and code readability in this
#define STATUS_REGISTER_SIZE 4
/* Number of machine registers. The only define actually required
- is NUM_REGS. The other definitions are used for documentation
+ is gdbarch_num_regs. The other definitions are used for documentation
purposes and code readability. */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
(and called PS for processor status) so the status bits can be cleared
#define FLAG_C 0x20000000
#define FLAG_V 0x10000000
-/* Prototypes for internal interfaces needed by more than one MD file. */
-int arm_pc_is_thumb_dummy (CORE_ADDR);
+/* Type of floating-point code in use by inferior. There are really 3 models
+ that are traditionally supported (plus the endianness issue), but gcc can
+ only generate 2 of those. The third is APCS_FLOAT, where arguments to
+ functions are passed in floating-point registers.
+
+ In addition to the traditional models, VFP adds two more.
+
+ If you update this enum, don't forget to update fp_model_strings in
+ arm-tdep.c. */
+
+enum arm_float_model
+{
+ ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
+ ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
+ ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
+ ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
+ ARM_FLOAT_VFP, /* Full VFP calling convention. */
+ ARM_FLOAT_LAST /* Keep at end. */
+};
+
+/* ABI used by the inferior. */
+enum arm_abi_kind
+{
+ ARM_ABI_AUTO,
+ ARM_ABI_APCS,
+ ARM_ABI_AAPCS,
+ ARM_ABI_LAST
+};
+
+/* Convention for returning structures. */
+
+enum struct_return
+{
+ pcc_struct_return, /* Return "short" structures in memory. */
+ reg_struct_return /* Return "short" structures in registers. */
+};
+
+/* Target-dependent structure in gdbarch. */
+struct gdbarch_tdep
+{
+ /* The ABI for this architecture. It should never be set to
+ ARM_ABI_AUTO. */
+ enum arm_abi_kind arm_abi;
+
+ enum arm_float_model fp_model; /* Floating point calling conventions. */
+
+ int have_fpa_registers; /* Does the target report the FPA registers? */
+
+ CORE_ADDR lowest_pc; /* Lowest address at which instructions
+ will appear. */
+
+ const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
+ int arm_breakpoint_size; /* And its size. */
+ const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn. */
+ int thumb_breakpoint_size; /* And its size. */
+
+ int jb_pc; /* Offset to PC value in jump buffer.
+ If this is negative, longjmp support
+ will be disabled. */
+ size_t jb_elt_size; /* And the size of each entry in the buf. */
+
+ /* Convention for returning structures. */
+ enum struct_return struct_return;
+
+ /* Cached core file helpers. */
+ struct regset *gregset, *fpregset;
+};
+
+
+
+#ifndef LOWEST_PC
+#define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
+#endif
+
+int arm_software_single_step (struct regcache *);
+
+/* Functions exported from armbsd-tdep.h. */
-int arm_pc_is_thumb (CORE_ADDR);
+/* Return the appropriate register set for the core section identified
+ by SECT_NAME and SECT_SIZE. */
-CORE_ADDR thumb_get_next_pc (CORE_ADDR);
+extern const struct regset *
+ armbsd_regset_from_core_section (struct gdbarch *gdbarch,
+ const char *sect_name, size_t sect_size);
-CORE_ADDR arm_get_next_pc (CORE_ADDR);
+#endif /* arm-tdep.h */