/* Common target dependent code for GDB on ARM systems.
- Copyright (C) 2002-2003, 2007-2012 Free Software Foundation, Inc.
+ Copyright (C) 2002-2013 Free Software Foundation, Inc.
This file is part of GDB.
bits. DWORD aligned they use 96 bits. */
#define FP_REGISTER_SIZE 12
+/* Say how long VFP double precision registers are. Used for documentation
+ purposes and code readability. These are fixed at 64 bits. */
+#define VFP_REGISTER_SIZE 8
+
/* Number of machine registers. The only define actually required
is gdbarch_num_regs. The other definitions are used for documentation
purposes and code readability. */
CORE_ADDR lowest_pc; /* Lowest address at which instructions
will appear. */
- const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
+ const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
int arm_breakpoint_size; /* And its size. */
- const char *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */
+ const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */
int thumb_breakpoint_size; /* And its size. */
/* If the Thumb breakpoint is an undefined instruction (which is
affected by IT blocks) rather than a BKPT instruction (which is
not), then we need a 32-bit Thumb breakpoint to preserve the
instruction count in IT blocks. */
- const char *thumb2_breakpoint;
+ const gdb_byte *thumb2_breakpoint;
int thumb2_breakpoint_size;
int jb_pc; /* Offset to PC value in jump buffer.