Contributed by the Center for Software Science at the
University of Utah (pa-gdb-bugs@cs.utah.edu). */
+/* Define offsets to access CPROC stack when it does not have
+ * a kernel thread.
+ */
+#define MACHINE_CPROC_SP_OFFSET 20
+#define MACHINE_CPROC_PC_OFFSET 16
+#define MACHINE_CPROC_FP_OFFSET 12
+
+/*
+ * Software defined PSW masks.
+ */
+#define PSW_SS 0x10000000 /* Kernel managed single step */
+
+/* Thread flavors used in re-setting the T bit.
+ * @@ this is also bad for cross debugging.
+ */
+#define TRACE_FLAVOR HP800_THREAD_STATE
+#define TRACE_FLAVOR_SIZE HP800_THREAD_STATE_COUNT
+#define TRACE_SET(x,state) \
+ ((struct hp800_thread_state *)state)->cr22 |= PSW_SS
+#define TRACE_CLEAR(x,state) \
+ ((((struct hp800_thread_state *)state)->cr22 &= ~PSW_SS), 1)
+
/* For OSF1 (Should be close if not identical to BSD, but I haven't
tested it yet):
} \
}
-/* OSF1 needs an extra trap. I assume for the emulator startup (?!?) */
-#define START_INFERIOR_TRAPS_EXPECTED 3
+/* OSF1 does not need the pc space queue restored. */
+#define NO_PC_SPACE_QUEUE_RESTORE
+
+/* The mach kernel uses the recovery counter to implement single
+ stepping. While this greatly simplifies the kernel support
+ necessary for single stepping, it unfortunately does the wrong
+ thing in the presense of a nullified instruction (gives control
+ back two insns after the nullifed insn). This is an artifact
+ of the HP architecture (recovery counter doesn't tick for
+ nullified insns).
+
+ Do our best to avoid losing in such situations. */
+#define INSTRUCTION_NULLIFIED \
+(({ \
+ int ipsw = (int)read_register(IPSW_REGNUM); \
+ if (ipsw & PSW_N) \
+ { \
+ int pcoqt = (int)read_register(PCOQ_TAIL_REGNUM); \
+ write_register(PCOQ_HEAD_REGNUM, pcoqt); \
+ write_register(PCOQ_TAIL_REGNUM, pcoqt + 0x4); \
+ write_register(IPSW_REGNUM, ipsw & ~(PSW_N | PSW_B | PSW_X)); \
+ stop_pc = pcoqt; \
+ } \
+ }), 0)
/* It's mostly just the common stuff. */
+
#include "pa/tm-hppa.h"