digs through the opcodes in order to find all possible targets.
Either one ordinary target or two targets for branches may be found. */
-static void
-cris_software_single_step (enum target_signal ignore, int insert_breakpoints)
+static int
+cris_software_single_step (struct regcache *regcache)
{
inst_env_type inst_env;
- if (insert_breakpoints)
+ /* Analyse the present instruction environment and insert
+ breakpoints. */
+ int status = find_step_target (&inst_env);
+ if (status == -1)
{
- /* Analyse the present instruction environment and insert
- breakpoints. */
- int status = find_step_target (&inst_env);
- if (status == -1)
- {
- /* Could not find a target. Things are likely to go downhill
- from here. */
- warning (_("CRIS software single step could not find a step target."));
- }
- else
- {
- /* Insert at most two breakpoints. One for the next PC content
- and possibly another one for a branch, jump, etc. */
- CORE_ADDR next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM];
- insert_single_step_breakpoint (next_pc);
- if (inst_env.branch_found
- && (CORE_ADDR) inst_env.branch_break_address != next_pc)
- {
- CORE_ADDR branch_target_address
- = (CORE_ADDR) inst_env.branch_break_address;
- insert_single_step_breakpoint (branch_target_address);
- }
- }
+ /* Could not find a target. Things are likely to go downhill
+ from here. */
+ warning (_("CRIS software single step could not find a step target."));
}
else
- remove_single_step_breakpoints ();
+ {
+ /* Insert at most two breakpoints. One for the next PC content
+ and possibly another one for a branch, jump, etc. */
+ CORE_ADDR next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM];
+ insert_single_step_breakpoint (next_pc);
+ if (inst_env.branch_found
+ && (CORE_ADDR) inst_env.branch_break_address != next_pc)
+ {
+ CORE_ADDR branch_target_address
+ = (CORE_ADDR) inst_env.branch_break_address;
+ insert_single_step_breakpoint (branch_target_address);
+ }
+ }
+
+ return 1;
}
/* Calculates the prefix value for quick offset addressing mode. */
/* Unpack an elf_gregset_t into GDB's register cache. */
static void
-supply_gregset (elf_gregset_t *gregsetp)
+cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
int i;
knows about the actual size of each register so that's no problem. */
for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
{
- regcache_raw_supply (current_regcache, i, (char *)®p[i]);
+ regcache_raw_supply (regcache, i, (char *)®p[i]);
}
if (tdep->cris_version == 32)
/* Needed to set pseudo-register PC for CRISv32. */
/* FIXME: If ERP is in a delay slot at this point then the PC will
be wrong. Issue a warning to alert the user. */
- regcache_raw_supply (current_regcache, PC_REGNUM,
+ regcache_raw_supply (regcache, PC_REGNUM,
(char *)®p[ERP_REGNUM]);
if (*(char *)®p[ERP_REGNUM] & 0x1)
regsets, until multi-arch core support is ready. */
static void
-fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
+fetch_core_registers (struct regcache *regcache,
+ char *core_reg_sect, unsigned core_reg_size,
int which, CORE_ADDR reg_addr)
{
elf_gregset_t gregset;
else
{
memcpy (&gregset, core_reg_sect, sizeof (gregset));
- supply_gregset (&gregset);
+ cris_supply_gregset (regcache, &gregset);
}
default: