/* Target-dependent code for Mitsubishi D10V, for GDB.
- Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc.
-This file is part of GDB.
+ This file is part of GDB.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
/* Contributed by Martin Hunt, hunt@cygnus.com */
#include "gdb_string.h"
#include "value.h"
#include "inferior.h"
-#include "dis-asm.h"
+#include "dis-asm.h"
#include "symfile.h"
#include "objfiles.h"
+#include "language.h"
+#include "arch-utils.h"
+
+#include "sim-d10v.h"
+
+#undef XMALLOC
+#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
struct frame_extra_info
-{
- CORE_ADDR return_pc;
- int frameless;
- int size;
-};
+ {
+ CORE_ADDR return_pc;
+ int frameless;
+ int size;
+ };
+
+struct gdbarch_tdep
+ {
+ int a0_regnum;
+ int nr_dmap_regs;
+ unsigned long (*dmap_register) (int nr);
+ unsigned long (*imap_register) (int nr);
+ int (*register_sim_regno) (int nr);
+ };
-/* these are the addresses the D10V-EVA board maps data */
-/* and instruction memory to. */
+/* These are the addresses the D10V-EVA board maps data and
+ instruction memory to. */
-#define DMEM_START 0x0000000
+#define DMEM_START 0x2000000
#define IMEM_START 0x1000000
#define STACK_START 0x0007ffe
-/* d10v register naming conventions */
+/* d10v register names. */
+
+enum
+ {
+ R0_REGNUM = 0,
+ LR_REGNUM = 13,
+ PSW_REGNUM = 16,
+ NR_IMAP_REGS = 2,
+ NR_A_REGS = 2
+ };
+#define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
+#define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
+
+/* d10v calling convention. */
#define ARG1_REGNUM R0_REGNUM
#define ARGN_REGNUM 3
static void d10v_eva_get_trace_data PARAMS ((void));
-static int prologue_find_regs PARAMS ((unsigned short op, struct frame_info *fi, CORE_ADDR addr));
+static int prologue_find_regs PARAMS ((unsigned short op, struct frame_info * fi, CORE_ADDR addr));
extern void d10v_frame_init_saved_regs PARAMS ((struct frame_info *));
-static void do_d10v_pop_frame PARAMS ((struct frame_info *fi));
-
-/* FIXME */
-extern void remote_d10v_translate_xfer_address PARAMS ((CORE_ADDR gdb_addr, int gdb_len, CORE_ADDR *rem_addr, int *rem_len));
+static void do_d10v_pop_frame PARAMS ((struct frame_info * fi));
int
d10v_frame_chain_valid (chain, frame)
CORE_ADDR chain;
- struct frame_info *frame; /* not used here */
+ struct frame_info *frame; /* not used here */
{
return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START);
}
+static CORE_ADDR
+d10v_stack_align (CORE_ADDR len)
+{
+ return (len + 1) & ~1;
+}
/* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
CORE_ADDR *pcptr;
int *lenptr;
{
- static unsigned char breakpoint [] = {0x2f, 0x90, 0x5e, 0x00};
+ static unsigned char breakpoint[] =
+ {0x2f, 0x90, 0x5e, 0x00};
*lenptr = sizeof (breakpoint);
return breakpoint;
}
-char *
-d10v_register_name (reg_nr)
- int reg_nr;
+/* Map the REG_NR onto an ascii name. Return NULL or an empty string
+ when the reg_nr isn't valid. */
+
+enum ts2_regnums
+ {
+ TS2_IMAP0_REGNUM = 32,
+ TS2_DMAP_REGNUM = 34,
+ TS2_NR_DMAP_REGS = 1,
+ TS2_A0_REGNUM = 35
+ };
+
+static char *
+d10v_ts2_register_name (int reg_nr)
+{
+ static char *register_names[] =
+ {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
+ "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
+ "imap0", "imap1", "dmap", "a0", "a1"
+ };
+ if (reg_nr < 0)
+ return NULL;
+ if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
+ return NULL;
+ return register_names[reg_nr];
+}
+
+enum ts3_regnums
+ {
+ TS3_IMAP0_REGNUM = 36,
+ TS3_DMAP0_REGNUM = 38,
+ TS3_NR_DMAP_REGS = 4,
+ TS3_A0_REGNUM = 32
+ };
+
+static char *
+d10v_ts3_register_name (int reg_nr)
{
- static char *register_names[] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10","r11","r12", "r13", "r14","r15",
- "psw","bpsw","pc","bpc", "cr4", "cr5", "cr6", "rpt_c",
- "rpt_s","rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
- "imap0","imap1","dmap","a0", "a1"
+ static char *register_names[] =
+ {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
+ "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
+ "a0", "a1",
+ "spi", "spu",
+ "imap0", "imap1",
+ "dmap0", "dmap1", "dmap2", "dmap3"
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
- return register_names [reg_nr];
+ return register_names[reg_nr];
+}
+
+/* Access the DMAP/IMAP registers in a target independant way. */
+
+static unsigned long
+d10v_ts2_dmap_register (int reg_nr)
+{
+ switch (reg_nr)
+ {
+ case 0:
+ case 1:
+ return 0x2000;
+ case 2:
+ return read_register (TS2_DMAP_REGNUM);
+ default:
+ return 0;
+ }
+}
+
+static unsigned long
+d10v_ts3_dmap_register (int reg_nr)
+{
+ return read_register (TS3_DMAP0_REGNUM + reg_nr);
+}
+
+static unsigned long
+d10v_dmap_register (int reg_nr)
+{
+ return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr);
}
+static unsigned long
+d10v_ts2_imap_register (int reg_nr)
+{
+ return read_register (TS2_IMAP0_REGNUM + reg_nr);
+}
+
+static unsigned long
+d10v_ts3_imap_register (int reg_nr)
+{
+ return read_register (TS3_IMAP0_REGNUM + reg_nr);
+}
+
+static unsigned long
+d10v_imap_register (int reg_nr)
+{
+ return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr);
+}
+
+/* MAP GDB's internal register numbering (determined by the layout fo
+ the REGISTER_BYTE array) onto the simulator's register
+ numbering. */
+
+static int
+d10v_ts2_register_sim_regno (int nr)
+{
+ if (nr >= TS2_IMAP0_REGNUM
+ && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS)
+ return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
+ if (nr == TS2_DMAP_REGNUM)
+ return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM;
+ if (nr >= TS2_A0_REGNUM
+ && nr < TS2_A0_REGNUM + NR_A_REGS)
+ return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM;
+ return nr;
+}
+
+static int
+d10v_ts3_register_sim_regno (int nr)
+{
+ if (nr >= TS3_IMAP0_REGNUM
+ && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS)
+ return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
+ if (nr >= TS3_DMAP0_REGNUM
+ && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS)
+ return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM;
+ if (nr >= TS3_A0_REGNUM
+ && nr < TS3_A0_REGNUM + NR_A_REGS)
+ return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM;
+ return nr;
+}
+
+int
+d10v_register_sim_regno (int nr)
+{
+ return gdbarch_tdep (current_gdbarch)->register_sim_regno (nr);
+}
/* Index within `registers' of the first byte of the space for
register REG_NR. */
d10v_register_byte (reg_nr)
int reg_nr;
{
- if (reg_nr > A0_REGNUM)
- return ((reg_nr - A0_REGNUM) * 8 + (A0_REGNUM * 2));
- else
+ if (reg_nr < A0_REGNUM)
return (reg_nr * 2);
+ else if (reg_nr < (A0_REGNUM + NR_A_REGS))
+ return (A0_REGNUM * 2
+ + (reg_nr - A0_REGNUM) * 8);
+ else
+ return (A0_REGNUM * 2
+ + NR_A_REGS * 8
+ + (reg_nr - A0_REGNUM - NR_A_REGS) * 2);
}
/* Number of bytes of storage in the actual machine representation for
d10v_register_raw_size (reg_nr)
int reg_nr;
{
- if (reg_nr >= A0_REGNUM)
+ if (reg_nr < A0_REGNUM)
+ return 2;
+ else if (reg_nr < (A0_REGNUM + NR_A_REGS))
return 8;
else
return 2;
d10v_register_virtual_size (reg_nr)
int reg_nr;
{
- if (reg_nr >= A0_REGNUM)
- return 8;
- else if (reg_nr == PC_REGNUM || reg_nr == SP_REGNUM)
- return 4;
- else
- return 2;
+ return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr));
}
/* Return the GDB type object for the "standard" data type
d10v_register_virtual_type (reg_nr)
int reg_nr;
{
- if (reg_nr >= A0_REGNUM)
- return builtin_type_long_long;
- else if (reg_nr == PC_REGNUM || reg_nr == SP_REGNUM)
- return builtin_type_long;
+ if (reg_nr >= A0_REGNUM
+ && reg_nr < (A0_REGNUM + NR_A_REGS))
+ return builtin_type_int64;
+ else if (reg_nr == PC_REGNUM
+ || reg_nr == SP_REGNUM)
+ return builtin_type_int32;
else
- return builtin_type_short;
+ return builtin_type_int16;
}
/* convert $pc and $sp to/from virtual addresses */
}
CORE_ADDR
-d10v_convert_daddr_to_raw(x)
+d10v_convert_daddr_to_raw (x)
CORE_ADDR x;
{
return ((x) & 0xffff);
Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
void
-d10v_store_return_value (type,valbuf)
+d10v_store_return_value (type, valbuf)
struct type *type;
char *valbuf;
{
d10v_saved_pc_after_call (frame)
struct frame_info *frame;
{
- return ((read_register(LR_REGNUM) << 2)
+ return ((read_register (LR_REGNUM) << 2)
| IMEM_START);
}
/* fill out fsr with the address of where each */
/* register was stored in the frame */
d10v_frame_init_saved_regs (fi);
-
+
/* now update the current registers with the old values */
- for (regnum = A0_REGNUM; regnum < A0_REGNUM+2 ; regnum++)
+ for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++)
{
if (fi->saved_regs[regnum])
{
- read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE(regnum));
- write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE(regnum));
+ read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum));
+ write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum));
}
}
for (regnum = 0; regnum < SP_REGNUM; regnum++)
{
if (fi->saved_regs[regnum])
{
- write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE(regnum)));
+ write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum)));
}
}
if (fi->saved_regs[PSW_REGNUM])
{
- write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE(PSW_REGNUM)));
+ write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM)));
}
write_register (PC_REGNUM, read_register (LR_REGNUM));
flush_cached_frames ();
}
-static int
+static int
check_prologue (op)
unsigned short op;
{
return 1;
/* st2w rn, @sp */
- if ((op & 0x7E3F) == 0x3A1E)
- return 1;
+ if ((op & 0x7E3F) == 0x3A1E)
+ return 1;
return 0;
}
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
{
sal = find_pc_line (func_addr, 0);
- if ( sal.end && sal.end < func_end)
+ if (sal.end && sal.end < func_end)
return sal.end;
}
-
- if (target_read_memory (pc, (char *)&op, 4))
+
+ if (target_read_memory (pc, (char *) &op, 4))
return pc; /* Can't access it -- assume no prologue. */
while (1)
{
- op = (unsigned long)read_memory_integer (pc, 4);
+ op = (unsigned long) read_memory_integer (pc, 4);
if ((op & 0xC0000000) == 0xC0000000)
{
/* long instruction */
- if ( ((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
- ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
- ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
+ if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
+ ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
+ ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
break;
}
else
{
op2 = (op & 0x3FFF8000) >> 15;
op1 = op & 0x7FFF;
- }
- else
+ }
+ else
{
op1 = (op & 0x3FFF8000) >> 15;
op2 = op & 0x7FFF;
}
- if (check_prologue(op1))
+ if (check_prologue (op1))
{
- if (!check_prologue(op2))
+ if (!check_prologue (op2))
{
/* if the previous opcode was really part of the prologue */
/* and not just a NOP, then we want to break after both instructions */
/* Given a GDB frame, determine the address of the calling function's frame.
This will be used to create a new GDB frame struct, and then
INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
-*/
+ */
CORE_ADDR
d10v_frame_chain (fi)
if (fi->extra_info->return_pc == IMEM_START
|| inside_entry_file (fi->extra_info->return_pc))
- return (CORE_ADDR)0;
+ return (CORE_ADDR) 0;
if (!fi->saved_regs[FP_REGNUM])
{
if (!fi->saved_regs[SP_REGNUM]
|| fi->saved_regs[SP_REGNUM] == STACK_START)
- return (CORE_ADDR)0;
-
+ return (CORE_ADDR) 0;
+
return fi->saved_regs[SP_REGNUM];
}
- if (!read_memory_unsigned_integer(fi->saved_regs[FP_REGNUM],
- REGISTER_RAW_SIZE(FP_REGNUM)))
- return (CORE_ADDR)0;
+ if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
+ REGISTER_RAW_SIZE (FP_REGNUM)))
+ return (CORE_ADDR) 0;
return D10V_MAKE_DADDR (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
- REGISTER_RAW_SIZE (FP_REGNUM)));
-}
+ REGISTER_RAW_SIZE (FP_REGNUM)));
+}
static int next_addr, uses_frame;
-static int
+static int
prologue_find_regs (op, fi, addr)
unsigned short op;
struct frame_info *fi;
n = (op & 0x1E0) >> 5;
next_addr -= 4;
fi->saved_regs[n] = next_addr;
- fi->saved_regs[n+1] = next_addr+2;
+ fi->saved_regs[n + 1] = next_addr + 2;
return 1;
}
{
n = (op & 0x1E0) >> 5;
fi->saved_regs[n] = next_addr;
- fi->saved_regs[n+1] = next_addr+2;
+ fi->saved_regs[n + 1] = next_addr + 2;
return 1;
}
uses_frame = 0;
while (1)
{
- op = (unsigned long)read_memory_integer (pc, 4);
+ op = (unsigned long) read_memory_integer (pc, 4);
if ((op & 0xC0000000) == 0xC0000000)
{
/* long instruction */
short offset = op & 0xFFFF;
short n = (op >> 20) & 0xF;
fi->saved_regs[n] = next_addr + offset;
- fi->saved_regs[n+1] = next_addr + offset + 2;
+ fi->saved_regs[n + 1] = next_addr + offset + 2;
}
else
break;
{
op2 = (op & 0x3FFF8000) >> 15;
op1 = op & 0x7FFF;
- }
- else
+ }
+ else
{
op1 = (op & 0x3FFF8000) >> 15;
op2 = op & 0x7FFF;
}
- if (!prologue_find_regs(op1, fi, pc) || !prologue_find_regs(op2, fi, pc))
+ if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc))
break;
}
pc += 4;
}
-
+
fi->extra_info->size = -next_addr;
if (!(fp & 0xffff))
- fp = D10V_MAKE_DADDR (read_register(SP_REGNUM));
+ fp = D10V_MAKE_DADDR (read_register (SP_REGNUM));
- for (i=0; i<NUM_REGS-1; i++)
+ for (i = 0; i < NUM_REGS - 1; i++)
if (fi->saved_regs[i])
{
- fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]);
+ fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]);
}
if (fi->saved_regs[LR_REGNUM])
}
else
{
- fi->extra_info->return_pc = D10V_MAKE_IADDR (read_register(LR_REGNUM));
+ fi->extra_info->return_pc = D10V_MAKE_IADDR (read_register (LR_REGNUM));
}
-
+
/* th SP is not normally (ever?) saved, but check anyway */
if (!fi->saved_regs[SP_REGNUM])
{
/* if the FP was saved, that means the current FP is valid, */
/* otherwise, it isn't being used, so we use the SP instead */
if (uses_frame)
- fi->saved_regs[SP_REGNUM] = read_register(FP_REGNUM) + fi->extra_info->size;
+ fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size;
else
{
fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size;
int from_tty;
{
int a;
- printf_filtered ("PC=%04x (0x%x) PSW=%04x RPT_S=%04x RPT_E=%04x RPT_C=%04x\n",
- read_register (PC_REGNUM), D10V_MAKE_IADDR (read_register (PC_REGNUM)),
- read_register (PSW_REGNUM),
- read_register (24),
- read_register (25),
- read_register (23));
- printf_filtered ("R0-R7 %04x %04x %04x %04x %04x %04x %04x %04x\n",
- read_register (0),
- read_register (1),
- read_register (2),
- read_register (3),
- read_register (4),
- read_register (5),
- read_register (6),
- read_register (7));
- printf_filtered ("R8-R15 %04x %04x %04x %04x %04x %04x %04x %04x\n",
- read_register (8),
- read_register (9),
- read_register (10),
- read_register (11),
- read_register (12),
- read_register (13),
- read_register (14),
- read_register (15));
- printf_filtered ("IMAP0 %04x IMAP1 %04x DMAP %04x\n",
- read_register (IMAP0_REGNUM),
- read_register (IMAP1_REGNUM),
- read_register (DMAP_REGNUM));
- printf_filtered ("A0-A1");
- for (a = A0_REGNUM; a <= A0_REGNUM + 1; a++)
+ printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
+ (long) read_register (PC_REGNUM),
+ (long) D10V_MAKE_IADDR (read_register (PC_REGNUM)),
+ (long) read_register (PSW_REGNUM),
+ (long) read_register (24),
+ (long) read_register (25),
+ (long) read_register (23));
+ printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
+ (long) read_register (0),
+ (long) read_register (1),
+ (long) read_register (2),
+ (long) read_register (3),
+ (long) read_register (4),
+ (long) read_register (5),
+ (long) read_register (6),
+ (long) read_register (7));
+ printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
+ (long) read_register (8),
+ (long) read_register (9),
+ (long) read_register (10),
+ (long) read_register (11),
+ (long) read_register (12),
+ (long) read_register (13),
+ (long) read_register (14),
+ (long) read_register (15));
+ for (a = 0; a < NR_IMAP_REGS; a++)
+ {
+ if (a > 0)
+ printf_filtered (" ");
+ printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a));
+ }
+ if (NR_DMAP_REGS == 1)
+ printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
+ else
+ {
+ for (a = 0; a < NR_DMAP_REGS; a++)
+ {
+ printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a));
+ }
+ printf_filtered ("\n");
+ }
+ printf_filtered ("A0-A%d", NR_A_REGS - 1);
+ for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++)
{
char num[MAX_REGISTER_RAW_SIZE];
int i;
printf_filtered (" ");
- read_register_gen (a, (char *)&num);
+ read_register_gen (a, (char *) &num);
for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++)
{
printf_filtered ("%02x", (num[i] & 0xff));
CORE_ADDR
d10v_read_fp ()
{
- return (D10V_MAKE_DADDR (read_register(FP_REGNUM)));
+ return (D10V_MAKE_DADDR (read_register (FP_REGNUM)));
}
/* Function: push_return_address (pc)
Set up the return address for the inferior function call.
Needed for targets where we don't actually execute a JSR/BSR instruction */
-
+
CORE_ADDR
d10v_push_return_address (pc, sp)
CORE_ADDR pc;
write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ()));
return sp;
}
-
+
/* When arguments must be pushed onto the stack, they go on in reverse
order. The below implements a FILO (stack) to do this. */
void *data;
};
-static struct stack_item *push_stack_item PARAMS ((struct stack_item *prev, void *contents, int len));
+static struct stack_item *push_stack_item PARAMS ((struct stack_item * prev, void *contents, int len));
static struct stack_item *
push_stack_item (prev, contents, len)
struct stack_item *prev;
return si;
}
-static struct stack_item *pop_stack_item PARAMS ((struct stack_item *si));
+static struct stack_item *pop_stack_item PARAMS ((struct stack_item * si));
static struct stack_item *
pop_stack_item (si)
struct stack_item *si;
int i;
int regnum = ARG1_REGNUM;
struct stack_item *si = NULL;
-
+
/* Fill in registers and arg lists */
for (i = 0; i < nargs; i++)
{
}
else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2)
/* value fits in remaining registers, store keeping left
- aligned */
+ aligned */
{
int b;
regnum = aligned_regnum;
else
{
/* arg will go onto stack */
- regnum = ARGN_REGNUM + 1;
+ regnum = ARGN_REGNUM + 1;
si = push_stack_item (si, contents, len);
}
}
write_memory (sp, si->data, si->len);
si = pop_stack_item (si);
}
-
+
return sp;
}
int num;
short snum;
snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
- store_address ( valbuf, 4, D10V_MAKE_IADDR(snum));
+ store_address (valbuf, 4, D10V_MAKE_IADDR (snum));
}
- else if (TYPE_CODE(type) == TYPE_CODE_PTR)
+ else if (TYPE_CODE (type) == TYPE_CODE_PTR)
{
/* pointer to data */
int num;
short snum;
snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
- store_address ( valbuf, 4, D10V_MAKE_DADDR(snum));
+ store_address (valbuf, 4, D10V_MAKE_DADDR (snum));
}
else
{
else
{
/* For return values of odd size, the first byte is in the
- least significant part of the first register. The
- remaining bytes in remaining registers. Interestingly,
- when such values are passed in, the last byte is in the
- most significant byte of that same register - wierd. */
+ least significant part of the first register. The
+ remaining bytes in remaining registers. Interestingly,
+ when such values are passed in, the last byte is in the
+ most significant byte of that same register - wierd. */
memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len);
}
}
}
+/* Translate a GDB virtual ADDR/LEN into a format the remote target
+ understands. Returns number of bytes that can be transfered
+ starting at TARG_ADDR. Return ZERO if no bytes can be transfered
+ (segmentation fault). Since the simulator knows all about how the
+ VM system works, we just call that to do the translation. */
+
+static void
+remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
+ CORE_ADDR *targ_addr, int *targ_len)
+{
+ long out_addr;
+ long out_len;
+ out_len = sim_d10v_translate_addr (memaddr, nr_bytes,
+ &out_addr,
+ d10v_dmap_register,
+ d10v_imap_register);
+ *targ_addr = out_addr;
+ *targ_len = out_len;
+}
+
+
/* The following code implements access to, and display of, the D10V's
instruction trace buffer. The buffer consists of 64K or more
4-byte words of data, of which each words includes an 8-bit count,
static int default_trace_show_source = 1;
-struct trace_buffer {
- int size;
- short *counts;
- CORE_ADDR *addrs;
-} trace_data;
+struct trace_buffer
+ {
+ int size;
+ short *counts;
+ CORE_ADDR *addrs;
+ }
+trace_data;
static void
trace_command (args, from_tty)
/* Clear the host-side trace buffer, allocating space if needed. */
trace_data.size = 0;
if (trace_data.counts == NULL)
- trace_data.counts = (short *) xmalloc (65536 * sizeof(short));
+ trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
if (trace_data.addrs == NULL)
- trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof(CORE_ADDR));
+ trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
tracing = 1;
for (i = 0; i < trace_data.size; ++i)
{
- printf_filtered ("%d: %d instruction%s at 0x%x\n",
- i, trace_data.counts[i],
+ printf_filtered ("%d: %d instruction%s at 0x%s\n",
+ i,
+ trace_data.counts[i],
(trace_data.counts[i] == 1 ? "" : "s"),
- trace_data.addrs[i]);
+ paddr_nz (trace_data.addrs[i]));
}
}
else
static int
print_insn (memaddr, stream)
CORE_ADDR memaddr;
- GDB_FILE *stream;
+ struct ui_file *stream;
{
/* If there's no disassembler, something is very wrong. */
if (tm_print_insn == NULL)
- abort ();
+ internal_error ("print_insn: no disassembler");
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
tm_print_insn_info.endian = BFD_ENDIAN_BIG;
if (!tracing)
return;
- tmpspace = xmalloc (65536 * sizeof(unsigned int));
+ tmpspace = xmalloc (65536 * sizeof (unsigned int));
last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
high = low;
}
- printf_filtered ("Dump of trace from %d to %d:\n", low, high);
+ printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
display_trace (low, high);
CORE_ADDR next_address;
trace_show_source = default_trace_show_source;
- if (!have_full_symbols () && !have_partial_symbols())
+ if (!have_full_symbols () && !have_partial_symbols ())
{
trace_show_source = 0;
printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
for (i = low; i < high; ++i)
{
next_address = trace_data.addrs[i];
- count = trace_data.counts[i];
+ count = trace_data.counts[i];
while (count-- > 0)
{
QUIT;
if (!suppress)
/* FIXME-32x64--assumes sal.pc fits in long. */
printf_filtered ("No source file for address %s.\n",
- local_hex_string((unsigned long) sal.pc));
+ local_hex_string ((unsigned long) sal.pc));
suppress = 1;
}
}
static gdbarch_init_ftype d10v_gdbarch_init;
+
static struct gdbarch *
d10v_gdbarch_init (info, arches)
struct gdbarch_info info;
struct gdbarch_list *arches;
{
- static LONGEST d10v_call_dummy_words[] = { 0 };
+ static LONGEST d10v_call_dummy_words[] =
+ {0};
struct gdbarch *gdbarch;
- int d10v_num_regs = 37;
+ int d10v_num_regs;
+ struct gdbarch_tdep *tdep;
+ gdbarch_register_name_ftype *d10v_register_name;
- /* there is only one d10v architecture */
+ /* Find a candidate among the list of pre-declared architectures. */
+ arches = gdbarch_list_lookup_by_info (arches, &info);
if (arches != NULL)
return arches->gdbarch;
- gdbarch = gdbarch_alloc (&info, NULL);
+
+ /* None found, create a new architecture from the information
+ provided. */
+ tdep = XMALLOC (struct gdbarch_tdep);
+ gdbarch = gdbarch_alloc (&info, tdep);
+
+ switch (info.bfd_arch_info->mach)
+ {
+ case bfd_mach_d10v_ts2:
+ d10v_num_regs = 37;
+ d10v_register_name = d10v_ts2_register_name;
+ tdep->a0_regnum = TS2_A0_REGNUM;
+ tdep->nr_dmap_regs = TS2_NR_DMAP_REGS;
+ tdep->register_sim_regno = d10v_ts2_register_sim_regno;
+ tdep->dmap_register = d10v_ts2_dmap_register;
+ tdep->imap_register = d10v_ts2_imap_register;
+ break;
+ default:
+ case bfd_mach_d10v_ts3:
+ d10v_num_regs = 42;
+ d10v_register_name = d10v_ts3_register_name;
+ tdep->a0_regnum = TS3_A0_REGNUM;
+ tdep->nr_dmap_regs = TS3_NR_DMAP_REGS;
+ tdep->register_sim_regno = d10v_ts3_register_sim_regno;
+ tdep->dmap_register = d10v_ts3_dmap_register;
+ tdep->imap_register = d10v_ts3_imap_register;
+ break;
+ }
set_gdbarch_read_pc (gdbarch, d10v_read_pc);
set_gdbarch_write_pc (gdbarch, d10v_write_pc);
set_gdbarch_frame_locals_address (gdbarch, d10v_frame_locals_address);
set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
+ set_gdbarch_stack_align (gdbarch, d10v_stack_align);
return gdbarch;
}
add_com ("regs", class_vars, show_regs, "Print all registers");
- add_com ("trace", class_support, trace_command,
+ add_com ("itrace", class_support, trace_command,
"Enable tracing of instruction execution.");
- add_com ("untrace", class_support, untrace_command,
+ add_com ("iuntrace", class_support, untrace_command,
"Disable tracing of instruction execution.");
- add_com ("tdisassemble", class_vars, tdisassemble_command,
+ add_com ("itdisassemble", class_vars, tdisassemble_command,
"Disassemble the trace buffer.\n\
Two optional arguments specify a range of trace buffer entries\n\
as reported by info trace (NOT addresses!).");
- add_info ("trace", trace_info,
+ add_info ("itrace", trace_info,
"Display info about the trace data buffer.");
- add_show_from_set (add_set_cmd ("tracedisplay", no_class,
- var_integer, (char *)&trace_display,
- "Set automatic display of trace.\n", &setlist),
+ add_show_from_set (add_set_cmd ("itracedisplay", no_class,
+ var_integer, (char *) &trace_display,
+ "Set automatic display of trace.\n", &setlist),
&showlist);
- add_show_from_set (add_set_cmd ("tracesource", no_class,
- var_integer, (char *)&default_trace_show_source,
- "Set display of source code with trace.\n", &setlist),
+ add_show_from_set (add_set_cmd ("itracesource", no_class,
+ var_integer, (char *) &default_trace_show_source,
+ "Set display of source code with trace.\n", &setlist),
&showlist);
-}
+}
projects / deliverable / binutils-gdb.git / blobdiff