S390: Add target descriptions for vector register sets

[deliverable/binutils-gdb.git] / gdb / doc / gdb.texinfo

diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index e84a251a68dfeec98f6253bc9af81e6d980bce04..19df52fdb77ce9f9d471925a0f955e8d3923c119 100644 (file)
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -39933,6 +39933,14 @@ The @samp{org.gnu.gdb.s390.tdb} feature is optional.  It should
 contain the 64-bit registers @samp{tdb0}, @samp{tac}, @samp{tct},
 @samp{atia}, and @samp{tr0} through @samp{tr15}.
 
+The @samp{org.gnu.gdb.s390.vx} feature is optional.  It should contain
+64-bit wide registers @samp{v0l} through @samp{v15l}, which will be
+combined by @value{GDBN} with the floating point registers @samp{f0}
+through @samp{f15} to present the 128-bit wide vector registers
+@samp{v0} through @samp{v15}.  In addition, this feature should
+contain the 128-bit wide vector registers @samp{v16} through
+@samp{v31}.
+
 @node TIC6x Features
 @subsection TMS320C6x Features
 @cindex target descriptions, TIC6x features