perror_with_name ("Unexpected byte order");
}
-
-#define INSTR_SC 0x44000002
-#define NR_spu_run 0x0116
-
-/* If the PPU thread is currently stopped on a spu_run system call,
- return to FD and ADDR the file handle and NPC parameter address
- used with the system call. Return non-zero if successful. */
-static int
-parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
-{
- CORE_ADDR curr_pc;
- int curr_insn;
- int curr_r0;
-
- if (register_size (regcache->tdesc, 0) == 4)
- {
- unsigned int pc, r0, r3, r4;
- collect_register_by_name (regcache, "pc", &pc);
- collect_register_by_name (regcache, "r0", &r0);
- collect_register_by_name (regcache, "orig_r3", &r3);
- collect_register_by_name (regcache, "r4", &r4);
- curr_pc = (CORE_ADDR) pc;
- curr_r0 = (int) r0;
- *fd = (int) r3;
- *addr = (CORE_ADDR) r4;
- }
- else
- {
- unsigned long pc, r0, r3, r4;
- collect_register_by_name (regcache, "pc", &pc);
- collect_register_by_name (regcache, "r0", &r0);
- collect_register_by_name (regcache, "orig_r3", &r3);
- collect_register_by_name (regcache, "r4", &r4);
- curr_pc = (CORE_ADDR) pc;
- curr_r0 = (int) r0;
- *fd = (int) r3;
- *addr = (CORE_ADDR) r4;
- }
-
- /* Fetch instruction preceding current NIP. */
- if ((*the_target->read_memory) (curr_pc - 4,
- (unsigned char *) &curr_insn, 4) != 0)
- return 0;
- /* It should be a "sc" instruction. */
- if (curr_insn != INSTR_SC)
- return 0;
- /* System call number should be NR_spu_run. */
- if (curr_r0 != NR_spu_run)
- return 0;
-
- return 1;
-}
-
static CORE_ADDR
ppc_get_pc (struct regcache *regcache)
{
- CORE_ADDR addr;
- int fd;
-
- if (parse_spufs_run (regcache, &fd, &addr))
- {
- unsigned int pc;
- (*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
- return ((CORE_ADDR)1 << 63)
- | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
- }
- else if (register_size (regcache->tdesc, 0) == 4)
+ if (register_size (regcache->tdesc, 0) == 4)
{
unsigned int pc;
collect_register_by_name (regcache, "pc", &pc);
static void
ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
{
- CORE_ADDR addr;
- int fd;
-
- if (parse_spufs_run (regcache, &fd, &addr))
- {
- unsigned int newpc = pc;
- (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
- }
- else if (register_size (regcache->tdesc, 0) == 4)
+ if (register_size (regcache->tdesc, 0) == 4)
{
unsigned int newpc = pc;
supply_register_by_name (regcache, "pc", &newpc);
}
}
-
-static int
-ppc_get_auxv (unsigned long type, unsigned long *valp)
-{
- const struct target_desc *tdesc = current_process ()->tdesc;
- int wordsize = register_size (tdesc, 0);
- unsigned char *data = (unsigned char *) alloca (2 * wordsize);
- int offset = 0;
-
- while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
- {
- if (wordsize == 4)
- {
- unsigned int *data_p = (unsigned int *)data;
- if (data_p[0] == type)
- {
- *valp = data_p[1];
- return 1;
- }
- }
- else
- {
- unsigned long *data_p = (unsigned long *)data;
- if (data_p[0] == type)
- {
- *valp = data_p[1];
- return 1;
- }
- }
-
- offset += 2 * wordsize;
- }
-
- *valp = 0;
- return 0;
-}
-
#ifndef __powerpc64__
static int ppc_regmap_adjusted;
#endif
{
unsigned int insn;
- if (where & ((CORE_ADDR)1 << 63))
- {
- char mem_annex[32];
- sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
- (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
- NULL, where & 0xffffffff, 4);
- if (insn == 0x3fff)
- return 1;
- }
- else
- {
- (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
- if (insn == ppc_breakpoint)
- return 1;
- /* If necessary, recognize more trap instructions here. GDB only uses
- the one. */
- }
+ (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
+ if (insn == ppc_breakpoint)
+ return 1;
+ /* If necessary, recognize more trap instructions here. GDB only uses
+ the one. */
return 0;
}
/* The value of current_process ()->tdesc needs to be set for this
call. */
- ppc_get_auxv (AT_HWCAP, &ppc_hwcap);
- ppc_get_auxv (AT_HWCAP2, &ppc_hwcap2);
+ ppc_hwcap = linux_get_hwcap (features.wordsize);
+ ppc_hwcap2 = linux_get_hwcap2 (features.wordsize);
features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
}
}
- if (ppc_hwcap & PPC_FEATURE_CELL)
- features.cell = true;
-
tdesc = ppc_linux_match_description (features);
/* On 32-bit machines, check for SPE registers.
#else
const int def_res = 0;
#endif
- unsigned long phdr;
+ CORE_ADDR phdr;
Elf64_Ehdr ehdr;
- if (!ppc_get_auxv (AT_PHDR, &phdr))
+ const struct target_desc *tdesc = current_process ()->tdesc;
+ int wordsize = register_size (tdesc, 0);
+
+ if (!linux_get_auxv (wordsize, AT_PHDR, &phdr))
return def_res;
/* Assume ELF header is at the beginning of the page where program headers
/* Jump over the unconditional branch. */
insn = (insn & ~0xfffc) | 0x8;
- write_inferior_memory (*to, (unsigned char *) &insn, 4);
+ target_write_memory (*to, (unsigned char *) &insn, 4);
*to += 4;
/* Build a unconditional branch and copy LK bit. */
insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
- write_inferior_memory (*to, (unsigned char *) &insn, 4);
+ target_write_memory (*to, (unsigned char *) &insn, 4);
*to += 4;
return;
bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
- write_inferior_memory (*to, (unsigned char *) &bdnz_insn, 4);
+ target_write_memory (*to, (unsigned char *) &bdnz_insn, 4);
*to += 4;
- write_inferior_memory (*to, (unsigned char *) &bf_insn, 4);
+ target_write_memory (*to, (unsigned char *) &bf_insn, 4);
*to += 4;
/* Build a unconditional branch and copy LK bit. */
insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
- write_inferior_memory (*to, (unsigned char *) &insn, 4);
+ target_write_memory (*to, (unsigned char *) &insn, 4);
*to += 4;
return;
/* Build a unconditional branch and copy LK bit. */
insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
- write_inferior_memory (*to, (unsigned char *) &insn, 4);
+ target_write_memory (*to, (unsigned char *) &insn, 4);
*to += 4;
return;
}
}
- write_inferior_memory (*to, (unsigned char *) &insn, 4);
+ target_write_memory (*to, (unsigned char *) &insn, 4);
*to += 4;
}
p += GEN_ADDI (p, 1, 1, frame_size);
/* Flush instructions to inferior memory. */
- write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
+ target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
/* Now, insert the original instruction to execute in the jump pad. */
*adjusted_insn_addr = buildaddr + (p - buf) * 4;
}
/* b <tpaddr+4> */
p += GEN_B (p, offset);
- write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
+ target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
*jump_entry = buildaddr + (p - buf) * 4;
/* The jump pad is now built. Wire in a jump to our jump pad. This
emit_insns (uint32_t *buf, int n)
{
n = n * sizeof (uint32_t);
- write_inferior_memory (current_insn_ptr, (unsigned char *) buf, n);
+ target_write_memory (current_insn_ptr, (unsigned char *) buf, n);
current_insn_ptr += n;
}
}
if (!emit_error)
- write_inferior_memory (from, (unsigned char *) &insn, 4);
+ target_write_memory (from, (unsigned char *) &insn, 4);
}
/* Table of emit ops for 32-bit. */
return PPC_TDESC_BASE;
if (tdesc == tdesc_powerpc_altivec64l)
return PPC_TDESC_ALTIVEC;
- if (tdesc == tdesc_powerpc_cell64l)
- return PPC_TDESC_CELL;
if (tdesc == tdesc_powerpc_vsx64l)
return PPC_TDESC_VSX;
if (tdesc == tdesc_powerpc_isa205_64l)
return PPC_TDESC_BASE;
if (tdesc == tdesc_powerpc_altivec32l)
return PPC_TDESC_ALTIVEC;
- if (tdesc == tdesc_powerpc_cell32l)
- return PPC_TDESC_CELL;
if (tdesc == tdesc_powerpc_vsx32l)
return PPC_TDESC_VSX;
if (tdesc == tdesc_powerpc_isa205_32l)
init_registers_powerpc_32l ();
init_registers_powerpc_altivec32l ();
- init_registers_powerpc_cell32l ();
init_registers_powerpc_vsx32l ();
init_registers_powerpc_isa205_32l ();
init_registers_powerpc_isa205_altivec32l ();
#if __powerpc64__
init_registers_powerpc_64l ();
init_registers_powerpc_altivec64l ();
- init_registers_powerpc_cell64l ();
init_registers_powerpc_vsx64l ();
init_registers_powerpc_isa205_64l ();
init_registers_powerpc_isa205_altivec64l ();
projects / deliverable / binutils-gdb.git / blobdiff