/* Intel 386 target-dependent stuff.
- Copyright (C) 1988-2015 Free Software Foundation, Inc.
+ Copyright (C) 1988-2016 Free Software Foundation, Inc.
This file is part of GDB.
return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
}
-/* Convert SVR4 register number REG to the appropriate register number
+/* Convert SVR4 DWARF register number REG to the appropriate register number
used by GDB. */
static int
-i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
case 45: return I386_GS_REGNUM;
}
- /* This will hopefully provoke a warning. */
- return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
+ return -1;
+}
+
+/* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
+ num_regs + num_pseudo_regs for other debug formats. */
+
+static int
+i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+{
+ int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
+
+ if (regnum == -1)
+ return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
+ return regnum;
}
\f
}
else if (i386_byte_regnum_p (gdbarch, regnum))
{
- /* Check byte pseudo registers last since this function will
- be called from amd64_pseudo_register_read, which handles
- byte pseudo registers differently. */
int gpnum = regnum - tdep->al_regnum;
/* Extract (always little endian). We read both lower and
}
else if (i386_byte_regnum_p (gdbarch, regnum))
{
- /* Check byte pseudo registers last since this function will
- be called from amd64_pseudo_register_read, which handles
- byte pseudo registers differently. */
int gpnum = regnum - tdep->al_regnum;
/* Read ... We read both lower and upper registers. */
internal_error (__FILE__, __LINE__, _("invalid regnum"));
}
}
+
+/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
+
+int
+i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
+ struct agent_expr *ax, int regnum)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (i386_mmx_regnum_p (gdbarch, regnum))
+ {
+ /* MMX to FPU register mapping depends on current TOS. Let's just
+ not care and collect everything... */
+ int i;
+
+ ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
+ for (i = 0; i < 8; i++)
+ ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
+ return 0;
+ }
+ else if (i386_bnd_regnum_p (gdbarch, regnum))
+ {
+ regnum -= tdep->bnd0_regnum;
+ ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
+ return 0;
+ }
+ else if (i386_k_regnum_p (gdbarch, regnum))
+ {
+ regnum -= tdep->k0_regnum;
+ ax_reg_mask (ax, tdep->k0_regnum + regnum);
+ return 0;
+ }
+ else if (i386_zmm_regnum_p (gdbarch, regnum))
+ {
+ regnum -= tdep->zmm0_regnum;
+ if (regnum < num_lower_zmm_regs)
+ {
+ ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
+ ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
+ }
+ else
+ {
+ ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
+ - num_lower_zmm_regs);
+ ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
+ - num_lower_zmm_regs);
+ }
+ ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
+ return 0;
+ }
+ else if (i386_ymm_regnum_p (gdbarch, regnum))
+ {
+ regnum -= tdep->ymm0_regnum;
+ ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
+ ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
+ return 0;
+ }
+ else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
+ {
+ regnum -= tdep->ymm16_regnum;
+ ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
+ ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
+ return 0;
+ }
+ else if (i386_word_regnum_p (gdbarch, regnum))
+ {
+ int gpnum = regnum - tdep->ax_regnum;
+
+ ax_reg_mask (ax, gpnum);
+ return 0;
+ }
+ else if (i386_byte_regnum_p (gdbarch, regnum))
+ {
+ int gpnum = regnum - tdep->al_regnum;
+
+ ax_reg_mask (ax, gpnum % 4);
+ return 0;
+ }
+ else
+ internal_error (__FILE__, __LINE__, _("invalid regnum"));
+ return 1;
+}
\f
/* Return the register number of the register allocated by GCC after
set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
/* Use the SVR4 register numbering scheme for DWARF 2. */
- set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
/* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
be in use on any of the supported i386 targets. */
set_gdbarch_pseudo_register_read_value (gdbarch,
i386_pseudo_register_read_value);
set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
+ set_gdbarch_ax_pseudo_register_collect (gdbarch,
+ i386_ax_pseudo_register_collect);
set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
return ret & MPX_BASE_MASK;
}
-/* Check if the current target is MPX enabled. */
-
-static int
+int
i386_mpx_enabled (void)
{
const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
bt_mask = (CORE_ADDR) MPX_BT_MASK;
if ( sizeof (CORE_ADDR) == 4)
- error (_("operation not supported"));
+ error (_("bound table examination not supported\
+ for 64-bit process with 32-bit GDB"));
}
else
{
if (!i386_mpx_enabled ())
{
- printf_unfiltered (_("Intel(R) Memory Protection Extensions not "
+ printf_unfiltered (_("Intel Memory Protection Extensions not "
"supported on this target.\n"));
return;
}
for (i = 0; i < 4; i++)
bt_entry[i] = read_memory_typed_address (bt_entry_addr
- + i * data_ptr_type->length,
+ + i * TYPE_LENGTH (data_ptr_type),
data_ptr_type);
i386_mpx_print_bounds (bt_entry);
struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
if (!i386_mpx_enabled ())
- error (_("Intel(R) Memory Protection Extensions not supported\
+ error (_("Intel Memory Protection Extensions not supported\
on this target."));
if (args == NULL)
bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
for (i = 0; i < 2; i++)
bt_entry[i] = read_memory_typed_address (bt_entry_addr
- + i * data_ptr_type->length,
+ + i * TYPE_LENGTH (data_ptr_type),
data_ptr_type);
bt_entry[0] = (uint64_t) lower;
bt_entry[1] = ~(uint64_t) upper;
for (i = 0; i < 2; i++)
- write_memory_unsigned_integer (bt_entry_addr + i * data_ptr_type->length,
- data_ptr_type->length, byte_order,
+ write_memory_unsigned_integer (bt_entry_addr
+ + i * TYPE_LENGTH (data_ptr_type),
+ TYPE_LENGTH (data_ptr_type), byte_order,
bt_entry[i]);
}
/* Add "mpx" prefix for the set commands. */
add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
-Set Intel(R) Memory Protection Extensions specific variables."),
+Set Intel Memory Protection Extensions specific variables."),
&mpx_set_cmdlist, "set mpx ",
0 /* allow-unknown */, &setlist);
/* Add "mpx" prefix for the show commands. */
add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
-Show Intel(R) Memory Protection Extensions specific variables."),
+Show Intel Memory Protection Extensions specific variables."),
&mpx_show_cmdlist, "show mpx ",
0 /* allow-unknown */, &showlist);