#include "command.h"
#include "dummy-frame.h"
#include "dwarf2-frame.h"
-#include "doublest.h"
#include "frame.h"
#include "frame-base.h"
#include "frame-unwind.h"
#include "symfile.h"
#include "symtab.h"
#include "target.h"
+#include "target-float.h"
#include "value.h"
#include "dis-asm.h"
#include "disasm.h"
#include "record.h"
#include "record-full.h"
-#include "features/i386/i386.c"
-#include "features/i386/i386-avx.c"
-#include "features/i386/i386-mpx.c"
-#include "features/i386/i386-avx-mpx.c"
-#include "features/i386/i386-avx-avx512.c"
-#include "features/i386/i386-avx-mpx-avx512-pku.c"
-#include "features/i386/i386-mmx.c"
+#include "target-descriptions.h"
+#include "arch/i386.h"
#include "ax.h"
#include "ax-gdb.h"
/* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
num_regs + num_pseudo_regs for other debug formats. */
-static int
+int
i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
return i386_jmp_p (insn);
}
-/* Some kernels may run one past a syscall insn, so we have to cope.
- Otherwise this is just simple_displaced_step_copy_insn. */
+/* Some kernels may run one past a syscall insn, so we have to cope. */
struct displaced_step_closure *
i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
struct regcache *regs)
{
size_t len = gdbarch_max_insn_length (gdbarch);
- gdb_byte *buf = (gdb_byte *) xmalloc (len);
+ i386_displaced_step_closure *closure = new i386_displaced_step_closure (len);
+ gdb_byte *buf = closure->buf.data ();
read_memory (from, buf, len);
displaced_step_dump_bytes (gdb_stdlog, buf, len);
}
- return (struct displaced_step_closure *) buf;
+ return closure;
}
/* Fix up the state of registers and memory after having single-stepped
void
i386_displaced_step_fixup (struct gdbarch *gdbarch,
- struct displaced_step_closure *closure,
+ struct displaced_step_closure *closure_,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
applying it. */
ULONGEST insn_offset = to - from;
- /* Since we use simple_displaced_step_copy_insn, our closure is a
- copy of the instruction. */
- gdb_byte *insn = (gdb_byte *) closure;
+ i386_displaced_step_closure *closure
+ = (i386_displaced_step_closure *) closure_;
+ gdb_byte *insn = closure->buf.data ();
/* The start of the insn, needed in case we see some prefixes. */
gdb_byte *insn_start = insn;
int write_pass;
int args_space = 0;
+ /* BND registers can be in arbitrary values at the moment of the
+ inferior call. This can cause boundary violations that are not
+ due to a real bug or even desired by the user. The best to be done
+ is set the BND registers to allow access to the whole memory, INIT
+ state, before pushing the inferior call. */
+ i387_reset_bnd_regs (gdbarch, regcache);
+
/* Determine the total space required for arguments and struct
return address in a first pass (allowing for 16-byte-aligned
arguments), then push arguments in a second pass. */
exactly how it would happen on the target itself, but it is
the best we can do. */
regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
- convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
+ target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type);
}
else
{
floating-point format used by the FPU. This is probably
not exactly how it would happen on the target itself, but
it is the best we can do. */
- convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
+ target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch));
regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
/* Set the top of the floating-point register stack to 7. The
static int
i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
+ struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
int mmxreg, fpreg;
ULONGEST fstat;
int tos;
int regnum,
struct value *result_value)
{
- gdb_byte raw_buf[MAX_REGISTER_SIZE];
+ gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
enum register_status status;
gdb_byte *buf = value_contents_raw (result_value);
i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, const gdb_byte *buf)
{
- gdb_byte raw_buf[MAX_REGISTER_SIZE];
+ gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
if (i386_mmx_regnum_p (gdbarch, regnum))
{
i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *gregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const gdb_byte *regs = (const gdb_byte *) gregs;
int i;
const struct regcache *regcache,
int regnum, void *gregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
gdb_byte *regs = (gdb_byte *) gregs;
int i;
i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *fpregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (len == I387_SIZEOF_FXSAVE)
const struct regcache *regcache,
int regnum, void *fpregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (len == I387_SIZEOF_FXSAVE)
gdb_assert (disassembly_flavor == att_flavor
|| disassembly_flavor == intel_flavor);
- /* FIXME: kettenis/20020915: Until disassembler_options is properly
- constified, cast to prevent a compiler warning. */
- info->disassembler_options = (char *) disassembly_flavor;
+ info->disassembler_options = disassembly_flavor;
- return print_insn_i386 (pc, info);
+ return default_print_insn (pc, info);
}
\f
i386_stap_is_single_operand);
set_gdbarch_stap_parse_special_token (gdbarch,
i386_stap_parse_special_token);
-
- set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
}
/* System V Release 4 (SVR4). */
tdep->jb_pc_offset = 20;
}
-/* DJGPP. */
-
-static void
-i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
-{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-
- /* DJGPP doesn't have any special frames for signal handlers. */
- tdep->sigtramp_p = NULL;
-
- tdep->jb_pc_offset = 36;
-
- /* DJGPP does not support the SSE registers. */
- if (! tdesc_has_registers (info.target_desc))
- tdep->tdesc = tdesc_i386_mmx;
-
- /* Native compiler is GCC, which uses the SVR4 register numbering
- even in COFF and STABS. See the comment in i386_gdbarch_init,
- before the calls to set_gdbarch_stab_reg_to_regnum and
- set_gdbarch_sdb_reg_to_regnum. */
- set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
- set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
-
- set_gdbarch_has_dos_based_file_system (gdbarch, 1);
-
- set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
-}
\f
/* i386 register groups. In addition to the normal groups, add "mmx"
uint32_t opcode;
uint8_t opcode8;
ULONGEST addr;
- gdb_byte buf[MAX_REGISTER_SIZE];
+ gdb_byte buf[I386_MAX_REGISTER_SIZE];
struct i386_record_s ir;
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
uint8_t rex_w = -1;
/* Get the x86 target description from INFO. */
tdesc = info.target_desc;
if (! tdesc_has_registers (tdesc))
- tdesc = tdesc_i386;
+ tdesc = i386_target_description (X86_XSTATE_SSE_MASK);
tdep->tdesc = tdesc;
tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
/* Hook in ABI-specific overrides, if they have been registered.
Note: If INFO specifies a 64 bit arch, this is where we turn
a 32-bit i386 into a 64-bit amd64. */
- info.tdep_info = tdesc_data;
+ info.tdesc_data = tdesc_data;
gdbarch_init_osabi (info, gdbarch);
if (!i386_validate_tdesc_p (tdep, tdesc_data))
return gdbarch;
}
-static enum gdb_osabi
-i386_coff_osabi_sniffer (bfd *abfd)
-{
- if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
- || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
- return GDB_OSABI_GO32;
-
- return GDB_OSABI_UNKNOWN;
-}
\f
/* Return the target description for a specified XSAVE feature mask. */
const struct target_desc *
i386_target_description (uint64_t xcr0)
{
- switch (xcr0 & X86_XSTATE_ALL_MASK)
- {
- case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK:
- return tdesc_i386_avx_mpx_avx512_pku;
- case X86_XSTATE_AVX_AVX512_MASK:
- return tdesc_i386_avx_avx512;
- case X86_XSTATE_AVX_MPX_MASK:
- return tdesc_i386_avx_mpx;
- case X86_XSTATE_MPX_MASK:
- return tdesc_i386_mpx;
- case X86_XSTATE_AVX_MASK:
- return tdesc_i386_avx;
- default:
- return tdesc_i386;
- }
+ static target_desc *i386_tdescs \
+ [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
+ target_desc **tdesc;
+
+ tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0]
+ [(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
+ [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
+ [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
+ [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0];
+
+ if (*tdesc == NULL)
+ *tdesc = i386_create_target_description (xcr0, false);
+
+ return *tdesc;
}
#define MPX_BASE_MASK (~(ULONGEST) 0xfff)
enum register_status regstatus;
rcache = get_current_regcache ();
- tdep = gdbarch_tdep (get_regcache_arch (rcache));
+ tdep = gdbarch_tdep (rcache->arch ());
regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
/* Implement the command "show mpx bound". */
static void
-i386_mpx_info_bounds (char *args, int from_tty)
+i386_mpx_info_bounds (const char *args, int from_tty)
{
CORE_ADDR bd_base = 0;
CORE_ADDR addr;
/* Implement the command "set mpx bound". */
static void
-i386_mpx_set_bounds (char *args, int from_tty)
+i386_mpx_set_bounds (const char *args, int from_tty)
{
CORE_ADDR bd_base = 0;
CORE_ADDR addr, lower, upper;
/* Helper function for the CLI commands. */
static void
-set_mpx_cmd (char *args, int from_tty)
+set_mpx_cmd (const char *args, int from_tty)
{
help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
}
/* Helper function for the CLI commands. */
static void
-show_mpx_cmd (char *args, int from_tty)
+show_mpx_cmd (const char *args, int from_tty)
{
cmd_show_list (mpx_show_cmdlist, from_tty, "");
}
-/* Provide a prototype to silence -Wmissing-prototypes. */
-void _initialize_i386_tdep (void);
-
void
_initialize_i386_tdep (void)
{
in the bound table.",
&mpx_set_cmdlist);
- gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
- i386_coff_osabi_sniffer);
-
gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
i386_svr4_init_abi);
- gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
- i386_go32_init_abi);
/* Initialize the i386-specific register groups. */
i386_init_reggroups ();
- /* Initialize the standard target descriptions. */
- initialize_tdesc_i386 ();
- initialize_tdesc_i386_mmx ();
- initialize_tdesc_i386_avx ();
- initialize_tdesc_i386_mpx ();
- initialize_tdesc_i386_avx_mpx ();
- initialize_tdesc_i386_avx_avx512 ();
- initialize_tdesc_i386_avx_mpx_avx512_pku ();
-
/* Tell remote stub that we support XML target description. */
register_remote_support_xml ("i386");
+
+#if GDB_SELF_TEST
+ struct
+ {
+ const char *xml;
+ uint64_t mask;
+ } xml_masks[] = {
+ { "i386/i386.xml", X86_XSTATE_SSE_MASK },
+ { "i386/i386-mmx.xml", X86_XSTATE_X87_MASK },
+ { "i386/i386-avx.xml", X86_XSTATE_AVX_MASK },
+ { "i386/i386-mpx.xml", X86_XSTATE_MPX_MASK },
+ { "i386/i386-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
+ { "i386/i386-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
+ { "i386/i386-avx-mpx-avx512-pku.xml",
+ X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
+ };
+
+ for (auto &a : xml_masks)
+ {
+ auto tdesc = i386_target_description (a.mask);
+
+ selftests::record_xml_tdesc (a.xml, tdesc);
+ }
+#endif /* GDB_SELF_TEST */
}