Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
- 2010 Free Software Foundation, Inc.
+ 2010, 2011 Free Software Foundation, Inc.
This file is part of GDB.
#include "dis-asm.h"
#include "disasm.h"
#include "remote.h"
-
+#include "exceptions.h"
#include "gdb_assert.h"
#include "gdb_string.h"
#include "i386-tdep.h"
#include "i387-tdep.h"
+#include "i386-xstate.h"
#include "record.h"
#include <stdint.h>
#include "features/i386/i386.c"
+#include "features/i386/i386-avx.c"
+#include "features/i386/i386-mmx.c"
/* Register names. */
"mxcsr"
};
+static const char *i386_ymm_names[] =
+{
+ "ymm0", "ymm1", "ymm2", "ymm3",
+ "ymm4", "ymm5", "ymm6", "ymm7",
+};
+
+static const char *i386_ymmh_names[] =
+{
+ "ymm0h", "ymm1h", "ymm2h", "ymm3h",
+ "ymm4h", "ymm5h", "ymm6h", "ymm7h",
+};
+
/* Register names for MMX pseudo-registers. */
static const char *i386_mmx_names[] =
return regnum >= 0 && regnum < tdep->num_dword_regs;
}
+static int
+i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int ymm0h_regnum = tdep->ymm0h_regnum;
+
+ if (ymm0h_regnum < 0)
+ return 0;
+
+ regnum -= ymm0h_regnum;
+ return regnum >= 0 && regnum < tdep->num_ymm_regs;
+}
+
+/* AVX register? */
+
+int
+i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int ymm0_regnum = tdep->ymm0_regnum;
+
+ if (ymm0_regnum < 0)
+ return 0;
+
+ regnum -= ymm0_regnum;
+ return regnum >= 0 && regnum < tdep->num_ymm_regs;
+}
+
/* SSE register? */
-static int
-i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum)
+int
+i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
- if (I387_NUM_XMM_REGS (tdep) == 0)
+ if (num_xmm_regs == 0)
return 0;
- return (I387_XMM0_REGNUM (tdep) <= regnum
- && regnum < I387_MXCSR_REGNUM (tdep));
+ regnum -= I387_XMM0_REGNUM (tdep);
+ return regnum >= 0 && regnum < num_xmm_regs;
}
static int
&& regnum < I387_XMM0_REGNUM (tdep));
}
+/* Return the name of register REGNUM, or the empty string if it is
+ an anonymous register. */
+
+static const char *
+i386_register_name (struct gdbarch *gdbarch, int regnum)
+{
+ /* Hide the upper YMM registers. */
+ if (i386_ymmh_regnum_p (gdbarch, regnum))
+ return "";
+
+ return tdesc_register_name (gdbarch, regnum);
+}
+
/* Return the name of register REGNUM. */
const char *
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (i386_mmx_regnum_p (gdbarch, regnum))
return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
+ else if (i386_ymm_regnum_p (gdbarch, regnum))
+ return i386_ymm_names[regnum - tdep->ymm0_regnum];
else if (i386_byte_regnum_p (gdbarch, regnum))
return i386_byte_names[regnum - tdep->al_regnum];
else if (i386_word_regnum_p (gdbarch, regnum))
else if (reg >= 21 && reg <= 28)
{
/* SSE registers. */
- return reg - 21 + I387_XMM0_REGNUM (tdep);
+ int ymm0_regnum = tdep->ymm0_regnum;
+
+ if (ymm0_regnum >= 0
+ && i386_xmm_regnum_p (gdbarch, reg))
+ return reg - 21 + ymm0_regnum;
+ else
+ return reg - 21 + I387_XMM0_REGNUM (tdep);
}
else if (reg >= 29 && reg <= 36)
{
static int
i386_absolute_jmp_p (const gdb_byte *insn)
{
- /* jmp far (absolute address in operand) */
+ /* jmp far (absolute address in operand). */
if (insn[0] == 0xea)
return 1;
if (insn[0] == 0xff)
{
- /* jump near, absolute indirect (/4) */
+ /* jump near, absolute indirect (/4). */
if ((insn[1] & 0x38) == 0x20)
return 1;
- /* jump far, absolute indirect (/5) */
+ /* jump far, absolute indirect (/5). */
if ((insn[1] & 0x38) == 0x28)
return 1;
}
static int
i386_absolute_call_p (const gdb_byte *insn)
{
- /* call far, absolute */
+ /* call far, absolute. */
if (insn[0] == 0x9a)
return 1;
if (insn[0] == 0xff)
{
- /* Call near, absolute indirect (/2) */
+ /* Call near, absolute indirect (/2). */
if ((insn[1] & 0x38) == 0x10)
return 1;
- /* Call far, absolute indirect (/3) */
+ /* Call far, absolute indirect (/3). */
if ((insn[1] & 0x38) == 0x18)
return 1;
}
{
switch (insn[0])
{
- case 0xc2: /* ret near, pop N bytes */
+ case 0xc2: /* ret near, pop N bytes. */
case 0xc3: /* ret near */
- case 0xca: /* ret far, pop N bytes */
+ case 0xca: /* ret far, pop N bytes. */
case 0xcb: /* ret far */
case 0xcf: /* iret */
return 1;
if (i386_absolute_call_p (insn))
return 1;
- /* call near, relative */
+ /* call near, relative. */
if (insn[0] == 0xe8)
return 1;
length in bytes. Otherwise, return zero. */
static int
-i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp)
+i386_syscall_p (const gdb_byte *insn, int *lengthp)
{
if (insn[0] == 0xcd)
{
return 0;
}
+/* Some kernels may run one past a syscall insn, so we have to cope.
+ Otherwise this is just simple_displaced_step_copy_insn. */
+
+struct displaced_step_closure *
+i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
+ CORE_ADDR from, CORE_ADDR to,
+ struct regcache *regs)
+{
+ size_t len = gdbarch_max_insn_length (gdbarch);
+ gdb_byte *buf = xmalloc (len);
+
+ read_memory (from, buf, len);
+
+ /* GDB may get control back after the insn after the syscall.
+ Presumably this is a kernel bug.
+ If this is a syscall, make sure there's a nop afterwards. */
+ {
+ int syscall_length;
+ gdb_byte *insn;
+
+ insn = i386_skip_prefixes (buf, len);
+ if (insn != NULL && i386_syscall_p (insn, &syscall_length))
+ insn[syscall_length] = NOP_OPCODE;
+ }
+
+ write_memory (to, buf, len);
+
+ if (debug_displaced)
+ {
+ fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
+ paddress (gdbarch, from), paddress (gdbarch, to));
+ displaced_step_dump_bytes (gdb_stdlog, buf, len);
+ }
+
+ return (struct displaced_step_closure *) buf;
+}
+
/* Fix up the state of registers and memory after having single-stepped
a displaced instruction. */
&& ! i386_ret_p (insn))
{
ULONGEST orig_eip;
- ULONGEST insn_len;
+ int insn_len;
regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
it unrelocated. Goodness help us if there are PC-relative
system calls. */
if (i386_syscall_p (insn, &insn_len)
- && orig_eip != to + (insn - insn_start) + insn_len)
+ && orig_eip != to + (insn - insn_start) + insn_len
+ /* GDB can get control back after the insn after the syscall.
+ Presumably this is a kernel bug.
+ i386_displaced_step_copy_insn ensures its a nop,
+ we add one to the length for it. */
+ && orig_eip != to + (insn - insn_start) + insn_len + 1)
{
if (debug_displaced)
fprintf_unfiltered (gdb_stdlog,
paddress (gdbarch, retaddr));
}
}
+
+static void
+append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
+{
+ target_write_memory (*to, buf, len);
+ *to += len;
+}
+
+static void
+i386_relocate_instruction (struct gdbarch *gdbarch,
+ CORE_ADDR *to, CORE_ADDR oldloc)
+{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ gdb_byte buf[I386_MAX_INSN_LEN];
+ int offset = 0, rel32, newrel;
+ int insn_length;
+ gdb_byte *insn = buf;
+
+ read_memory (oldloc, buf, I386_MAX_INSN_LEN);
+
+ insn_length = gdb_buffered_insn_length (gdbarch, insn,
+ I386_MAX_INSN_LEN, oldloc);
+
+ /* Get past the prefixes. */
+ insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
+
+ /* Adjust calls with 32-bit relative addresses as push/jump, with
+ the address pushed being the location where the original call in
+ the user program would return to. */
+ if (insn[0] == 0xe8)
+ {
+ gdb_byte push_buf[16];
+ unsigned int ret_addr;
+
+ /* Where "ret" in the original code will return to. */
+ ret_addr = oldloc + insn_length;
+ push_buf[0] = 0x68; /* pushq $... */
+ memcpy (&push_buf[1], &ret_addr, 4);
+ /* Push the push. */
+ append_insns (to, 5, push_buf);
+
+ /* Convert the relative call to a relative jump. */
+ insn[0] = 0xe9;
+
+ /* Adjust the destination offset. */
+ rel32 = extract_signed_integer (insn + 1, 4, byte_order);
+ newrel = (oldloc - *to) + rel32;
+ store_signed_integer (insn + 1, 4, byte_order, newrel);
+
+ if (debug_displaced)
+ fprintf_unfiltered (gdb_stdlog,
+ "Adjusted insn rel32=%s at %s to"
+ " rel32=%s at %s\n",
+ hex_string (rel32), paddress (gdbarch, oldloc),
+ hex_string (newrel), paddress (gdbarch, *to));
+
+ /* Write the adjusted jump into its displaced location. */
+ append_insns (to, 5, insn);
+ return;
+ }
+
+ /* Adjust jumps with 32-bit relative addresses. Calls are already
+ handled above. */
+ if (insn[0] == 0xe9)
+ offset = 1;
+ /* Adjust conditional jumps. */
+ else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
+ offset = 2;
+
+ if (offset)
+ {
+ rel32 = extract_signed_integer (insn + offset, 4, byte_order);
+ newrel = (oldloc - *to) + rel32;
+ store_signed_integer (insn + offset, 4, byte_order, newrel);
+ if (debug_displaced)
+ fprintf_unfiltered (gdb_stdlog,
+ "Adjusted insn rel32=%s at %s to"
+ " rel32=%s at %s\n",
+ hex_string (rel32), paddress (gdbarch, oldloc),
+ hex_string (newrel), paddress (gdbarch, *to));
+ }
+
+ /* Write the adjusted instructions into their displaced
+ location. */
+ append_insns (to, insn_length, buf);
+}
+
\f
#ifdef I386_REGNO_TO_SYMMETRY
#error "The Sequent Symmetry is no longer supported."
{
/* Base address. */
CORE_ADDR base;
+ int base_p;
LONGEST sp_offset;
CORE_ADDR pc;
cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
/* Base address. */
+ cache->base_p = 0;
cache->base = 0;
cache->sp_offset = -4;
cache->pc = 0;
long delta = 0;
int data16 = 0;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
+
if (op == 0x66)
{
data16 = 1;
if (current_pc <= pc)
return pc;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
if (op != 0x58) /* popl %eax */
return pc;
- target_read_memory (pc + 1, buf, 4);
+ if (target_read_memory (pc + 1, buf, 4))
+ return pc;
+
if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
return pc;
gdb_byte buf[8];
gdb_byte op;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
if (op == 0x68 || op == 0x6a)
{
struct i386_insn *insn;
gdb_byte op;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return NULL;
for (insn = skip_insns; insn->len > 0; insn++)
{
gdb_assert (insn->len > 1);
gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
- target_read_memory (pc + 1, buf, insn->len - 1);
+ if (target_read_memory (pc + 1, buf, insn->len - 1))
+ return NULL;
+
for (i = 1; i < insn->len; i++)
{
if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
struct i386_insn i386_frame_setup_skip_insns[] =
{
- /* Check for `movb imm8, r' and `movl imm32, r'.
+ /* Check for `movb imm8, r' and `movl imm32, r'.
??? Should we handle 16-bit operand-sizes here? */
gdb_byte op;
int check = 1;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
while (check)
{
if (op == 0x90)
{
pc += 1;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
check = 1;
}
/* Ignore no-op instruction `mov %edi, %edi'.
else if (op == 0x8b)
{
- target_read_memory (pc + 1, &op, 1);
+ if (target_read_memory (pc + 1, &op, 1))
+ return pc;
+
if (op == 0xff)
{
pc += 2;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
+
check = 1;
}
}
if (limit <= pc)
return limit;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
if (op == 0x55) /* pushl %ebp */
{
if (limit <= pc + skip)
return limit;
- target_read_memory (pc + skip, &op, 1);
+ if (target_read_memory (pc + skip, &op, 1))
+ return pc + skip;
/* Check for `movl %esp, %ebp' -- can be written in two ways. */
switch (op)
NOTE: You can't subtract a 16-bit immediate from a 32-bit
reg, so we don't have to worry about a data16 prefix. */
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
if (op == 0x83)
{
/* `subl' with 8-bit immediate. */
offset -= cache->locals;
for (i = 0; i < 8 && pc < current_pc; i++)
{
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
if (op < 0x50 || op > 0x57)
break;
for (i = 0; i < 6; i++)
{
- target_read_memory (pc + i, &op, 1);
+ if (target_read_memory (pc + i, &op, 1))
+ return pc;
+
if (pic_pat[i] != op)
break;
}
{
int delta = 6;
- target_read_memory (pc + delta, &op, 1);
+ if (target_read_memory (pc + delta, &op, 1))
+ return pc;
if (op == 0x89) /* movl %ebx, x(%ebp) */
{
else /* Unexpected instruction. */
delta = 0;
- target_read_memory (pc + delta, &op, 1);
+ if (target_read_memory (pc + delta, &op, 1))
+ return pc;
}
/* addl y,%ebx */
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte op;
- target_read_memory (pc, &op, 1);
+ if (target_read_memory (pc, &op, 1))
+ return pc;
if (op == 0xe8)
{
gdb_byte buf[4];
/* Normal frames. */
-static struct i386_frame_cache *
-i386_frame_cache (struct frame_info *this_frame, void **this_cache)
+static void
+i386_frame_cache_1 (struct frame_info *this_frame,
+ struct i386_frame_cache *cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- struct i386_frame_cache *cache;
gdb_byte buf[4];
int i;
- if (*this_cache)
- return *this_cache;
-
- cache = i386_alloc_frame_cache ();
- *this_cache = cache;
+ cache->pc = get_frame_func (this_frame);
/* In principle, for normal frames, %ebp holds the frame pointer,
which holds the base address for the current stack frame.
get_frame_register (this_frame, I386_EBP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 4, byte_order);
if (cache->base == 0)
- return cache;
+ return;
/* For normal frames, %eip is stored at 4(%ebp). */
cache->saved_regs[I386_EIP_REGNUM] = 4;
- cache->pc = get_frame_func (this_frame);
if (cache->pc != 0)
i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
cache);
- if (cache->saved_sp_reg != -1)
- {
- /* Saved stack pointer has been saved. */
- get_frame_register (this_frame, cache->saved_sp_reg, buf);
- cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
- }
-
if (cache->locals < 0)
{
/* We didn't find a valid frame, which means that CACHE->base
if (cache->saved_sp_reg != -1)
{
+ /* Saved stack pointer has been saved. */
+ get_frame_register (this_frame, cache->saved_sp_reg, buf);
+ cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
+
/* We're halfway aligning the stack. */
cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
cache->saved_regs[I386_EBP_REGNUM] = 0;
}
+ if (cache->saved_sp_reg != -1)
+ {
+ /* Saved stack pointer has been saved (but the SAVED_SP_REG
+ register may be unavailable). */
+ if (cache->saved_sp == 0
+ && frame_register_read (this_frame, cache->saved_sp_reg, buf))
+ cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
+ }
/* Now that we have the base address for the stack frame we can
calculate the value of %esp in the calling frame. */
- if (cache->saved_sp == 0)
+ else if (cache->saved_sp == 0)
cache->saved_sp = cache->base + 8;
/* Adjust all the saved registers such that they contain addresses
if (cache->saved_regs[i] != -1)
cache->saved_regs[i] += cache->base;
+ cache->base_p = 1;
+}
+
+static struct i386_frame_cache *
+i386_frame_cache (struct frame_info *this_frame, void **this_cache)
+{
+ volatile struct gdb_exception ex;
+ struct i386_frame_cache *cache;
+
+ if (*this_cache)
+ return *this_cache;
+
+ cache = i386_alloc_frame_cache ();
+ *this_cache = cache;
+
+ TRY_CATCH (ex, RETURN_MASK_ERROR)
+ {
+ i386_frame_cache_1 (this_frame, cache);
+ }
+ if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
+ throw_exception (ex);
+
return cache;
}
(*this_id) = frame_id_build (cache->base + 8, cache->pc);
}
+static enum unwind_stop_reason
+i386_frame_unwind_stop_reason (struct frame_info *this_frame,
+ void **this_cache)
+{
+ struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
+
+ if (!cache->base_p)
+ return UNWIND_UNAVAILABLE;
+
+ /* This marks the outermost frame. */
+ if (cache->base == 0)
+ return UNWIND_OUTERMOST;
+
+ return UNWIND_NO_REASON;
+}
+
static struct value *
i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
int regnum)
if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
- if (regnum == I386_ESP_REGNUM && cache->saved_sp)
- return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
+ if (regnum == I386_ESP_REGNUM)
+ {
+ /* If the SP has been saved, but we don't know where, then this
+ means that SAVED_SP_REG register was found unavailable back
+ when we built the cache. */
+ if (cache->saved_sp == 0 && cache->saved_sp_reg != -1)
+ return frame_unwind_got_register (this_frame, regnum,
+ cache->saved_sp_reg);
+ else
+ return frame_unwind_got_constant (this_frame, regnum,
+ cache->saved_sp);
+ }
if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
return frame_unwind_got_memory (this_frame, regnum,
static const struct frame_unwind i386_frame_unwind =
{
NORMAL_FRAME,
+ i386_frame_unwind_stop_reason,
i386_frame_this_id,
i386_frame_prev_register,
NULL,
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ volatile struct gdb_exception ex;
struct i386_frame_cache *cache;
gdb_byte buf[4];
cache = i386_alloc_frame_cache ();
*this_cache = cache;
- /* Cache base will be %esp plus cache->sp_offset (-4). */
- get_frame_register (this_frame, I386_ESP_REGNUM, buf);
- cache->base = extract_unsigned_integer (buf, 4,
- byte_order) + cache->sp_offset;
+ TRY_CATCH (ex, RETURN_MASK_ERROR)
+ {
+ /* Cache base will be %esp plus cache->sp_offset (-4). */
+ get_frame_register (this_frame, I386_ESP_REGNUM, buf);
+ cache->base = extract_unsigned_integer (buf, 4,
+ byte_order) + cache->sp_offset;
+
+ /* Cache pc will be the frame func. */
+ cache->pc = get_frame_pc (this_frame);
- /* Cache pc will be the frame func. */
- cache->pc = get_frame_pc (this_frame);
+ /* The saved %esp will be at cache->base plus 8. */
+ cache->saved_sp = cache->base + 8;
- /* The saved %esp will be at cache->base plus 8. */
- cache->saved_sp = cache->base + 8;
+ /* The saved %eip will be at cache->base plus 4. */
+ cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
- /* The saved %eip will be at cache->base plus 4. */
- cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
+ cache->base_p = 1;
+ }
+ if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
+ throw_exception (ex);
return cache;
}
+static enum unwind_stop_reason
+i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
+ void **this_cache)
+{
+ struct i386_frame_cache *cache
+ = i386_epilogue_frame_cache (this_frame, this_cache);
+
+ if (!cache->base_p)
+ return UNWIND_UNAVAILABLE;
+
+ return UNWIND_NO_REASON;
+}
+
static void
i386_epilogue_frame_this_id (struct frame_info *this_frame,
void **this_cache,
struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame,
this_cache);
+ if (!cache->base_p)
+ return;
+
(*this_id) = frame_id_build (cache->base + 8, cache->pc);
}
static const struct frame_unwind i386_epilogue_frame_unwind =
{
NORMAL_FRAME,
+ i386_epilogue_frame_unwind_stop_reason,
i386_epilogue_frame_this_id,
i386_frame_prev_register,
NULL,
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ volatile struct gdb_exception ex;
struct i386_frame_cache *cache;
CORE_ADDR addr;
gdb_byte buf[4];
cache = i386_alloc_frame_cache ();
- get_frame_register (this_frame, I386_ESP_REGNUM, buf);
- cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
-
- addr = tdep->sigcontext_addr (this_frame);
- if (tdep->sc_reg_offset)
+ TRY_CATCH (ex, RETURN_MASK_ERROR)
{
- int i;
+ get_frame_register (this_frame, I386_ESP_REGNUM, buf);
+ cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
- gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
+ addr = tdep->sigcontext_addr (this_frame);
+ if (tdep->sc_reg_offset)
+ {
+ int i;
- for (i = 0; i < tdep->sc_num_regs; i++)
- if (tdep->sc_reg_offset[i] != -1)
- cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
- }
- else
- {
- cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
- cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
+ gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
+
+ for (i = 0; i < tdep->sc_num_regs; i++)
+ if (tdep->sc_reg_offset[i] != -1)
+ cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
+ }
+ else
+ {
+ cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
+ cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
+ }
+
+ cache->base_p = 1;
}
+ if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
+ throw_exception (ex);
*this_cache = cache;
return cache;
}
+static enum unwind_stop_reason
+i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
+ void **this_cache)
+{
+ struct i386_frame_cache *cache =
+ i386_sigtramp_frame_cache (this_frame, this_cache);
+
+ if (!cache->base_p)
+ return UNWIND_UNAVAILABLE;
+
+ return UNWIND_NO_REASON;
+}
+
static void
i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
struct frame_id *this_id)
struct i386_frame_cache *cache =
i386_sigtramp_frame_cache (this_frame, this_cache);
+ if (!cache->base_p)
+ return;
+
/* See the end of i386_push_dummy_call. */
(*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
}
static const struct frame_unwind i386_sigtramp_frame_unwind =
{
SIGTRAMP_FRAME,
+ i386_sigtramp_frame_unwind_stop_reason,
i386_sigtramp_frame_this_id,
i386_sigtramp_frame_prev_register,
NULL,
}
else
internal_error (__FILE__, __LINE__,
- _("Cannot extract return value of %d bytes long."), len);
+ _("Cannot extract return value of %d bytes long."),
+ len);
}
}
return tdep->i387_ext_type;
}
+/* Construct vector type for pseudo YMM registers. We can't use
+ tdesc_find_type since YMM isn't described in target description. */
+
+static struct type *
+i386_ymm_type (struct gdbarch *gdbarch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (!tdep->i386_ymm_type)
+ {
+ const struct builtin_type *bt = builtin_type (gdbarch);
+
+ /* The type we're building is this: */
+#if 0
+ union __gdb_builtin_type_vec256i
+ {
+ int128_t uint128[2];
+ int64_t v2_int64[4];
+ int32_t v4_int32[8];
+ int16_t v8_int16[16];
+ int8_t v16_int8[32];
+ double v2_double[4];
+ float v4_float[8];
+ };
+#endif
+
+ struct type *t;
+
+ t = arch_composite_type (gdbarch,
+ "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
+ append_composite_type_field (t, "v8_float",
+ init_vector_type (bt->builtin_float, 8));
+ append_composite_type_field (t, "v4_double",
+ init_vector_type (bt->builtin_double, 4));
+ append_composite_type_field (t, "v32_int8",
+ init_vector_type (bt->builtin_int8, 32));
+ append_composite_type_field (t, "v16_int16",
+ init_vector_type (bt->builtin_int16, 16));
+ append_composite_type_field (t, "v8_int32",
+ init_vector_type (bt->builtin_int32, 8));
+ append_composite_type_field (t, "v4_int64",
+ init_vector_type (bt->builtin_int64, 4));
+ append_composite_type_field (t, "v2_int128",
+ init_vector_type (bt->builtin_int128, 2));
+
+ TYPE_VECTOR (t) = 1;
+ TYPE_NAME (t) = "builtin_type_vec256i";
+ tdep->i386_ymm_type = t;
+ }
+
+ return tdep->i386_ymm_type;
+}
+
/* Construct vector type for MMX registers. */
static struct type *
i386_mmx_type (struct gdbarch *gdbarch)
}
/* Return the GDB type object for the "standard" data type of data in
- register REGNUM. */
+ register REGNUM. */
static struct type *
i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
{
if (i386_mmx_regnum_p (gdbarch, regnum))
return i386_mmx_type (gdbarch);
+ else if (i386_ymm_regnum_p (gdbarch, regnum))
+ return i386_ymm_type (gdbarch);
else
{
const struct builtin_type *bt = builtin_type (gdbarch);
return (I387_ST0_REGNUM (tdep) + fpreg);
}
-void
+enum register_status
i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, gdb_byte *buf)
{
gdb_byte raw_buf[MAX_REGISTER_SIZE];
+ enum register_status status;
if (i386_mmx_regnum_p (gdbarch, regnum))
{
int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
/* Extract (always little endian). */
- regcache_raw_read (regcache, fpnum, raw_buf);
+ status = regcache_raw_read (regcache, fpnum, raw_buf);
+ if (status != REG_VALID)
+ return status;
memcpy (buf, raw_buf, register_size (gdbarch, regnum));
}
else
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- if (i386_word_regnum_p (gdbarch, regnum))
+ if (i386_ymm_regnum_p (gdbarch, regnum))
+ {
+ regnum -= tdep->ymm0_regnum;
+
+ /* Extract (always little endian). Read lower 128bits. */
+ status = regcache_raw_read (regcache,
+ I387_XMM0_REGNUM (tdep) + regnum,
+ raw_buf);
+ if (status != REG_VALID)
+ return status;
+ memcpy (buf, raw_buf, 16);
+ /* Read upper 128bits. */
+ status = regcache_raw_read (regcache,
+ tdep->ymm0h_regnum + regnum,
+ raw_buf);
+ if (status != REG_VALID)
+ return status;
+ memcpy (buf + 16, raw_buf, 16);
+ }
+ else if (i386_word_regnum_p (gdbarch, regnum))
{
int gpnum = regnum - tdep->ax_regnum;
/* Extract (always little endian). */
- regcache_raw_read (regcache, gpnum, raw_buf);
+ status = regcache_raw_read (regcache, gpnum, raw_buf);
+ if (status != REG_VALID)
+ return status;
memcpy (buf, raw_buf, 2);
}
else if (i386_byte_regnum_p (gdbarch, regnum))
/* Extract (always little endian). We read both lower and
upper registers. */
- regcache_raw_read (regcache, gpnum % 4, raw_buf);
+ status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
+ if (status != REG_VALID)
+ return status;
if (gpnum >= 4)
memcpy (buf, raw_buf + 1, 1);
else
else
internal_error (__FILE__, __LINE__, _("invalid regnum"));
}
+
+ return REG_VALID;
}
void
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- if (i386_word_regnum_p (gdbarch, regnum))
+ if (i386_ymm_regnum_p (gdbarch, regnum))
+ {
+ regnum -= tdep->ymm0_regnum;
+
+ /* ... Write lower 128bits. */
+ regcache_raw_write (regcache,
+ I387_XMM0_REGNUM (tdep) + regnum,
+ buf);
+ /* ... Write upper 128bits. */
+ regcache_raw_write (regcache,
+ tdep->ymm0h_regnum + regnum,
+ buf + 16);
+ }
+ else if (i386_word_regnum_p (gdbarch, regnum))
{
int gpnum = regnum - tdep->ax_regnum;
needs any special handling. */
static int
-i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
+i386_convert_register_p (struct gdbarch *gdbarch,
+ int regnum, struct type *type)
{
int len = TYPE_LENGTH (type);
/* Read a value of type TYPE from register REGNUM in frame FRAME, and
return its contents in TO. */
-static void
+static int
i386_register_to_value (struct frame_info *frame, int regnum,
- struct type *type, gdb_byte *to)
+ struct type *type, gdb_byte *to,
+ int *optimizedp, int *unavailablep)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
int len = TYPE_LENGTH (type);
- /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
- available in FRAME (i.e. if it wasn't saved)? */
-
if (i386_fp_regnum_p (gdbarch, regnum))
- {
- i387_register_to_value (frame, regnum, type, to);
- return;
- }
+ return i387_register_to_value (frame, regnum, type, to,
+ optimizedp, unavailablep);
/* Read a value spread across multiple registers. */
gdb_assert (regnum != -1);
gdb_assert (register_size (gdbarch, regnum) == 4);
- get_frame_register (frame, regnum, to);
+ if (!get_frame_register_bytes (frame, regnum, 0,
+ register_size (gdbarch, regnum),
+ to, optimizedp, unavailablep))
+ return 0;
+
regnum = i386_next_regnum (regnum);
len -= 4;
to += 4;
}
+
+ *optimizedp = *unavailablep = 0;
+ return 1;
}
/* Write the contents FROM of a value of type TYPE into register
i387_collect_fsave (regcache, regnum, fpregs);
}
+/* Similar to i386_supply_fpregset, but use XSAVE extended state. */
+
+static void
+i386_supply_xstateregset (const struct regset *regset,
+ struct regcache *regcache, int regnum,
+ const void *xstateregs, size_t len)
+{
+ i387_supply_xsave (regcache, regnum, xstateregs);
+}
+
+/* Similar to i386_collect_fpregset , but use XSAVE extended state. */
+
+static void
+i386_collect_xstateregset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *xstateregs, size_t len)
+{
+ i387_collect_xsave (regcache, regnum, xstateregs, 1);
+}
+
/* Return the appropriate register set for the core section identified
by SECT_NAME and SECT_SIZE. */
return tdep->fpregset;
}
+ if (strcmp (sect_name, ".reg-xstate") == 0)
+ {
+ if (tdep->xstateregset == NULL)
+ tdep->xstateregset = regset_alloc (gdbarch,
+ i386_supply_xstateregset,
+ i386_collect_xstateregset);
+
+ return tdep->xstateregset;
+ }
+
return NULL;
}
\f
tdep->jb_pc_offset = 36;
/* DJGPP does not support the SSE registers. */
- tdep->num_xmm_regs = 0;
- set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I387_NUM_REGS);
+ if (! tdesc_has_registers (info.target_desc))
+ tdep->tdesc = tdesc_i386_mmx;
/* Native compiler is GCC, which uses the SVR4 register numbering
even in COFF and STABS. See the comment in i386_gdbarch_init,
set_gdbarch_sdb_reg_to_regnum. */
set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
+
+ set_gdbarch_has_dos_based_file_system (gdbarch, 1);
}
\f
i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *group)
{
- int sse_regnum_p, fp_regnum_p, mmx_regnum_p, byte_regnum_p,
- word_regnum_p, dword_regnum_p;
+ const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
+ ymm_regnum_p, ymmh_regnum_p;
/* Don't include pseudo registers, except for MMX, in any register
groups. */
- byte_regnum_p = i386_byte_regnum_p (gdbarch, regnum);
- if (byte_regnum_p)
+ if (i386_byte_regnum_p (gdbarch, regnum))
return 0;
- word_regnum_p = i386_word_regnum_p (gdbarch, regnum);
- if (word_regnum_p)
+ if (i386_word_regnum_p (gdbarch, regnum))
return 0;
- dword_regnum_p = i386_dword_regnum_p (gdbarch, regnum);
- if (dword_regnum_p)
+ if (i386_dword_regnum_p (gdbarch, regnum))
return 0;
mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
if (group == i386_mmx_reggroup)
return mmx_regnum_p;
- sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum)
- || i386_mxcsr_regnum_p (gdbarch, regnum));
+ xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
+ mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
if (group == i386_sse_reggroup)
- return sse_regnum_p;
+ return xmm_regnum_p || mxcsr_regnum_p;
+
+ ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
if (group == vector_reggroup)
- return mmx_regnum_p || sse_regnum_p;
+ return (mmx_regnum_p
+ || ymm_regnum_p
+ || mxcsr_regnum_p
+ || (xmm_regnum_p
+ && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
+ == I386_XSTATE_SSE_MASK)));
fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
|| i386_fpc_regnum_p (gdbarch, regnum));
if (group == float_reggroup)
return fp_regnum_p;
+ /* For "info reg all", don't include upper YMM registers nor XMM
+ registers when AVX is supported. */
+ ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
+ if (group == all_reggroup
+ && ((xmm_regnum_p
+ && (tdep->xcr0 & I386_XSTATE_AVX))
+ || ymmh_regnum_p))
+ return 0;
+
if (group == general_reggroup)
return (!fp_regnum_p
&& !mmx_regnum_p
- && !sse_regnum_p
- && !byte_regnum_p
- && !word_regnum_p
- && !dword_regnum_p);
+ && !mxcsr_regnum_p
+ && !xmm_regnum_p
+ && !ymm_regnum_p
+ && !ymmh_regnum_p);
return default_register_reggroup_p (gdbarch, regnum, group);
}
};
/* Parse "modrm" part in current memory address that irp->addr point to
- Return -1 if something wrong. */
+ Return -1 if something wrong. */
static int
i386_record_modrm (struct i386_record_s *irp)
/* Get the memory address that current instruction write to and set it to
the argument "addr".
- Return -1 if something wrong. */
+ Return -1 if something wrong. */
static int
i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
/* Record the value of the memory that willbe changed in current instruction
to "record_arch_list".
- Return -1 if something wrong. */
+ Return -1 if something wrong. */
static int
i386_record_lea_modrm (struct i386_record_s *irp)
if (irp->override >= 0)
{
- warning (_("Process record ignores the memory change "
- "of instruction at address %s because it "
- "can't get the value of the segment register."),
- paddress (gdbarch, irp->orig_addr));
+ if (record_memory_query)
+ {
+ int q;
+
+ target_terminal_ours ();
+ q = yquery (_("\
+Process record ignores the memory change of instruction at address %s\n\
+because it can't get the value of the segment register.\n\
+Do you want to stop the program?"),
+ paddress (gdbarch, irp->orig_addr));
+ target_terminal_inferior ();
+ if (q)
+ return -1;
+ }
+
return 0;
}
}
/* Record the push operation to "record_arch_list".
- Return -1 if something wrong. */
+ Return -1 if something wrong. */
static int
i386_record_push (struct i386_record_s *irp, int size)
#define I386_SAVE_FPU_ENV 0xfffe
#define I386_SAVE_FPU_ENV_REG_STACK 0xffff
-/* Record the value of floating point registers which will be changed by the
- current instruction to "record_arch_list". Return -1 if something is wrong.
-*/
+/* Record the value of floating point registers which will be changed
+ by the current instruction to "record_arch_list". Return -1 if
+ something is wrong. */
static int i386_record_floats (struct gdbarch *gdbarch,
struct i386_record_s *ir,
/* Parse the current instruction and record the values of the registers and
memory that will be changed in current instruction to "record_arch_list".
- Return -1 if something wrong. */
+ Return -1 if something wrong. */
#define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
else if (ir.regmap[X86_RECORD_R8_REGNUM])
ir.aflag = 2;
- /* now check op code */
+ /* Now check op code. */
opcode = (uint32_t) opcode8;
reswitch:
switch (opcode)
case 0xa3:
if (ir.override >= 0)
{
- warning (_("Process record ignores the memory change "
- "of instruction at address %s because "
- "it can't get the value of the segment "
- "register."),
- paddress (gdbarch, ir.orig_addr));
+ if (record_memory_query)
+ {
+ int q;
+
+ target_terminal_ours ();
+ q = yquery (_("\
+Process record ignores the memory change of instruction at address %s\n\
+because it can't get the value of the segment register.\n\
+Do you want to stop the program?"),
+ paddress (gdbarch, ir.orig_addr));
+ target_terminal_inferior ();
+ if (q)
+ return -1;
+ }
}
else
{
ir.addr -= 1;
goto no_support;
}
+ /* FALLTHROUGH */
case 0x0fb2: /* lss Gv */
case 0x0fb4: /* lfs Gv */
case 0x0fb5: /* lgs Gv */
ir.reg |= ((opcode & 7) << 3);
if (ir.mod != 3)
{
- /* Memory. */
+ /* Memory. */
uint64_t addr64;
if (i386_record_lea_modrm_addr (&ir, &addr64))
if (ir.aflag && (es != ds))
{
/* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
- warning (_("Process record ignores the memory "
- "change of instruction at address %s "
- "because it can't get the value of the "
- "ES segment register."),
- paddress (gdbarch, ir.orig_addr));
+ if (record_memory_query)
+ {
+ int q;
+
+ target_terminal_ours ();
+ q = yquery (_("\
+Process record ignores the memory change of instruction at address %s\n\
+because it can't get the value of the segment register.\n\
+Do you want to stop the program?"),
+ paddress (gdbarch, ir.orig_addr));
+ target_terminal_inferior ();
+ if (q)
+ return -1;
+ }
}
else
{
ir.addr -= 1;
goto no_support;
}
+ /* FALLTHROUGH */
case 0xf5: /* cmc */
case 0xf8: /* clc */
case 0xf9: /* stc */
break;
case 0x0f31: /* rdtsc */
- printf_unfiltered (_("Process record does not support "
- "instruction rdtsc.\n"));
- ir.addr -= 2;
- goto no_support;
+ I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+ I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
break;
case 0x0f34: /* sysenter */
}
if (ir.override >= 0)
{
- warning (_("Process record ignores the memory "
- "change of instruction at "
- "address %s because it can't get "
- "the value of the segment "
- "register."),
- paddress (gdbarch, ir.orig_addr));
+ if (record_memory_query)
+ {
+ int q;
+
+ target_terminal_ours ();
+ q = yquery (_("\
+Process record ignores the memory change of instruction at address %s\n\
+because it can't get the value of the segment register.\n\
+Do you want to stop the program?"),
+ paddress (gdbarch, ir.orig_addr));
+ target_terminal_inferior ();
+ if (q)
+ return -1;
+ }
}
else
{
/* sidt */
if (ir.override >= 0)
{
- warning (_("Process record ignores the memory "
- "change of instruction at "
- "address %s because it can't get "
- "the value of the segment "
- "register."),
- paddress (gdbarch, ir.orig_addr));
+ if (record_memory_query)
+ {
+ int q;
+
+ target_terminal_ours ();
+ q = yquery (_("\
+Process record ignores the memory change of instruction at address %s\n\
+because it can't get the value of the segment register.\n\
+Do you want to stop the program?"),
+ paddress (gdbarch, ir.orig_addr));
+ target_terminal_inferior ();
+ if (q)
+ return -1;
+ }
}
else
{
record_arch_list_add_reg (ir.regcache, i);
for (i = I387_XMM0_REGNUM (tdep);
- i386_sse_regnum_p (gdbarch, i); i++)
+ i386_xmm_regnum_p (gdbarch, i); i++)
record_arch_list_add_reg (ir.regcache, i);
if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
case 0x660f3804: /* pmaddubsw */
case 0x660f3805: /* phsubw */
case 0x660f3806: /* phsubd */
- case 0x660f3807: /* phaddsw */
+ case 0x660f3807: /* phsubsw */
case 0x660f3808: /* psignb */
case 0x660f3809: /* psignw */
case 0x660f380a: /* psignd */
case 0x660f63: /* packsswb */
case 0x660f64: /* pcmpgtb */
case 0x660f65: /* pcmpgtw */
- case 0x660f66: /* pcmpgtl */
+ case 0x660f66: /* pcmpgtd */
case 0x660f67: /* packuswb */
case 0x660f68: /* punpckhbw */
case 0x660f69: /* punpckhwd */
case 0xf30f70: /* pshufhw */
case 0x660f74: /* pcmpeqb */
case 0x660f75: /* pcmpeqw */
- case 0x660f76: /* pcmpeql */
+ case 0x660f76: /* pcmpeqd */
case 0x660f7c: /* haddpd */
case 0xf20f7c: /* haddps */
case 0x660f7d: /* hsubpd */
case 0x660fed: /* paddsw */
case 0x660fee: /* pmaxsw */
case 0x660fef: /* pxor */
- case 0x660ff0: /* lddqu */
+ case 0xf20ff0: /* lddqu */
case 0x660ff1: /* psllw */
case 0x660ff2: /* pslld */
case 0x660ff3: /* psllq */
case 0x660ff6: /* psadbw */
case 0x660ff8: /* psubb */
case 0x660ff9: /* psubw */
- case 0x660ffa: /* psubl */
+ case 0x660ffa: /* psubd */
case 0x660ffb: /* psubq */
case 0x660ffc: /* paddb */
case 0x660ffd: /* paddw */
- case 0x660ffe: /* paddl */
+ case 0x660ffe: /* paddd */
if (i386_record_modrm (&ir))
return -1;
ir.reg |= rex_r;
- if (!i386_sse_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
+ if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
goto no_support;
record_arch_list_add_reg (ir.regcache,
I387_XMM0_REGNUM (tdep) + ir.reg);
|| opcode == 0x0f17 || opcode == 0x660f17)
goto no_support;
ir.rm |= ir.rex_b;
- if (!i386_sse_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
+ if (!i386_xmm_regnum_p (gdbarch,
+ I387_XMM0_REGNUM (tdep) + ir.rm))
goto no_support;
record_arch_list_add_reg (ir.regcache,
I387_XMM0_REGNUM (tdep) + ir.rm);
case 0x0f3804: /* pmaddubsw */
case 0x0f3805: /* phsubw */
case 0x0f3806: /* phsubd */
- case 0x0f3807: /* phaddsw */
+ case 0x0f3807: /* phsubsw */
case 0x0f3808: /* psignb */
case 0x0f3809: /* psignw */
case 0x0f380a: /* psignd */
case 0x0f63: /* packsswb */
case 0x0f64: /* pcmpgtb */
case 0x0f65: /* pcmpgtw */
- case 0x0f66: /* pcmpgtl */
+ case 0x0f66: /* pcmpgtd */
case 0x0f67: /* packuswb */
case 0x0f68: /* punpckhbw */
case 0x0f69: /* punpckhwd */
case 0x0f70: /* pshufw */
case 0x0f74: /* pcmpeqb */
case 0x0f75: /* pcmpeqw */
- case 0x0f76: /* pcmpeql */
+ case 0x0f76: /* pcmpeqd */
case 0x0fc4: /* pinsrw */
case 0x0fd1: /* psrlw */
case 0x0fd2: /* psrld */
case 0x0ff6: /* psadbw */
case 0x0ff8: /* psubb */
case 0x0ff9: /* psubw */
- case 0x0ffa: /* psubl */
+ case 0x0ffa: /* psubd */
case 0x0ffb: /* psubq */
case 0x0ffc: /* paddb */
case 0x0ffd: /* paddw */
- case 0x0ffe: /* paddl */
+ case 0x0ffe: /* paddd */
if (i386_record_modrm (&ir))
return -1;
if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
if (i386_record_modrm (&ir))
return -1;
ir.rm |= ir.rex_b;
- if (!i386_sse_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
+ if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
goto no_support;
record_arch_list_add_reg (ir.regcache,
I387_XMM0_REGNUM (tdep) + ir.rm);
if (ir.mod == 3)
{
ir.rm |= ir.rex_b;
- if (!i386_sse_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
+ if (!i386_xmm_regnum_p (gdbarch,
+ I387_XMM0_REGNUM (tdep) + ir.rm))
goto no_support;
record_arch_list_add_reg (ir.regcache,
I387_XMM0_REGNUM (tdep) + ir.rm);
/* Return a bit of target-specific detail to add to the caller's
generic failure message. */
if (msg)
- *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
+ *msg = xstrprintf (_("; instruction is only %d bytes long, "
+ "need at least %d bytes for the jump"),
len, jumplen);
return 0;
}
struct tdesc_arch_data *tdesc_data)
{
const struct target_desc *tdesc = tdep->tdesc;
- const struct tdesc_feature *feature_core, *feature_vector;
+ const struct tdesc_feature *feature_core;
+ const struct tdesc_feature *feature_sse, *feature_avx;
int i, num_regs, valid_p;
if (! tdesc_has_registers (tdesc))
/* Get core registers. */
feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
+ if (feature_core == NULL)
+ return 0;
/* Get SSE registers. */
- feature_vector = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
+ feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
- if (feature_core == NULL || feature_vector == NULL)
- return 0;
+ /* Try AVX registers. */
+ feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
valid_p = 1;
+ /* The XCR0 bits. */
+ if (feature_avx)
+ {
+ /* AVX register description requires SSE register description. */
+ if (!feature_sse)
+ return 0;
+
+ tdep->xcr0 = I386_XSTATE_AVX_MASK;
+
+ /* It may have been set by OSABI initialization function. */
+ if (tdep->num_ymm_regs == 0)
+ {
+ tdep->ymmh_register_names = i386_ymmh_names;
+ tdep->num_ymm_regs = 8;
+ tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
+ }
+
+ for (i = 0; i < tdep->num_ymm_regs; i++)
+ valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
+ tdep->ymm0h_regnum + i,
+ tdep->ymmh_register_names[i]);
+ }
+ else if (feature_sse)
+ tdep->xcr0 = I386_XSTATE_SSE_MASK;
+ else
+ {
+ tdep->xcr0 = I386_XSTATE_X87_MASK;
+ tdep->num_xmm_regs = 0;
+ }
+
num_regs = tdep->num_core_regs;
for (i = 0; i < num_regs; i++)
valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
tdep->register_names[i]);
- /* Need to include %mxcsr, so add one. */
- num_regs += tdep->num_xmm_regs + 1;
- for (; i < num_regs; i++)
- valid_p &= tdesc_numbered_register (feature_vector, tdesc_data, i,
- tdep->register_names[i]);
+ if (feature_sse)
+ {
+ /* Need to include %mxcsr, so add one. */
+ num_regs += tdep->num_xmm_regs + 1;
+ for (; i < num_regs; i++)
+ valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
+ tdep->register_names[i]);
+ }
return valid_p;
}
struct tdesc_arch_data *tdesc_data;
const struct target_desc *tdesc;
int mm0_regnum;
+ int ymm0_regnum;
/* If there is already a candidate, use it. */
arches = gdbarch_list_lookup_by_info (arches, &info);
tdep->fpregset = NULL;
tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
+ tdep->xstateregset = NULL;
+
/* The default settings include the FPU registers, the MMX registers
and the SSE registers. This can be overridden for a specific ABI
by adjusting the members `st0_regnum', `mm0_regnum' and
`num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
- will show up in the output of "info all-registers". Ideally we
- should try to autodetect whether they are available, such that we
- can prevent "info all-registers" from displaying registers that
- aren't available.
-
- NOTE: kevinb/2003-07-13: ... if it's a choice between printing
- [the SSE registers] always (even when they don't exist) or never
- showing them to the user (even when they do exist), I prefer the
- former over the latter. */
+ will show up in the output of "info all-registers". */
tdep->st0_regnum = I386_ST0_REGNUM;
tdep->sc_pc_offset = -1;
tdep->sc_sp_offset = -1;
+ tdep->xsave_xcr0_offset = -1;
+
tdep->record_regmap = i386_record_regmap;
/* The format used for `long double' on almost all i386 targets is
set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
- /* The default ABI includes general-purpose registers,
- floating-point registers, and the SSE registers. */
- set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS);
+ /* Override the normal target description method to make the AVX
+ upper halves anonymous. */
+ set_gdbarch_register_name (gdbarch, i386_register_name);
+
+ /* Even though the default ABI only includes general-purpose registers,
+ floating-point registers and the SSE registers, we have to leave a
+ gap for the upper AVX registers. */
+ set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
/* Get the x86 target description from INFO. */
tdesc = info.target_desc;
tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
tdep->register_names = i386_register_names;
+ /* No upper YMM registers. */
+ tdep->ymmh_register_names = NULL;
+ tdep->ymm0h_regnum = -1;
+
tdep->num_byte_regs = 8;
tdep->num_word_regs = 8;
tdep->num_dword_regs = 0;
tdep->num_mmx_regs = 8;
+ tdep->num_ymm_regs = 0;
tdesc_data = tdesc_data_alloc ();
+ set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
+
/* Hook in ABI-specific overrides, if they have been registered. */
info.tdep_info = (void *) tdesc_data;
gdbarch_init_osabi (info, gdbarch);
+ if (!i386_validate_tdesc_p (tdep, tdesc_data))
+ {
+ tdesc_data_cleanup (tdesc_data);
+ xfree (tdep);
+ gdbarch_free (gdbarch);
+ return NULL;
+ }
+
/* Wire in pseudo registers. Number of pseudo registers may be
changed. */
set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
+ tdep->num_word_regs
+ tdep->num_dword_regs
- + tdep->num_mmx_regs));
+ + tdep->num_mmx_regs
+ + tdep->num_ymm_regs));
/* Target description may be changed. */
tdesc = tdep->tdesc;
- if (!i386_validate_tdesc_p (tdep, tdesc_data))
- {
- tdesc_data_cleanup (tdesc_data);
- xfree (tdep);
- gdbarch_free (gdbarch);
- return NULL;
- }
-
tdesc_use_registers (gdbarch, tdesc, tdesc_data);
/* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
tdep->al_regnum = gdbarch_num_regs (gdbarch);
tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
- mm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
+ ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
if (tdep->num_dword_regs)
{
- /* Support dword pseudo-registesr if it hasn't been disabled, */
- tdep->eax_regnum = mm0_regnum;
- mm0_regnum = tdep->eax_regnum + tdep->num_dword_regs;
+ /* Support dword pseudo-register if it hasn't been disabled. */
+ tdep->eax_regnum = ymm0_regnum;
+ ymm0_regnum += tdep->num_dword_regs;
}
else
tdep->eax_regnum = -1;
+ mm0_regnum = ymm0_regnum;
+ if (tdep->num_ymm_regs)
+ {
+ /* Support YMM pseudo-register if it is available. */
+ tdep->ymm0_regnum = ymm0_regnum;
+ mm0_regnum += tdep->num_ymm_regs;
+ }
+ else
+ tdep->ymm0_regnum = -1;
+
if (tdep->num_mmx_regs != 0)
{
- /* Support MMX pseudo-registesr if MMX hasn't been disabled, */
+ /* Support MMX pseudo-register if MMX hasn't been disabled. */
tdep->mm0_regnum = mm0_regnum;
}
else
/* Initialize the standard target descriptions. */
initialize_tdesc_i386 ();
+ initialize_tdesc_i386_mmx ();
+ initialize_tdesc_i386_avx ();
/* Tell remote stub that we support XML target description. */
register_remote_support_xml ("i386");