reg_struct_return /* Return "short" structures in registers. */
};
-/* Register classes as defined in the AMD x86-64 psABI. */
-
-enum amd64_reg_class
-{
- AMD64_INTEGER,
- AMD64_SSE,
- AMD64_SSEUP,
- AMD64_X87,
- AMD64_X87UP,
- AMD64_COMPLEX_X87,
- AMD64_NO_CLASS,
- AMD64_MEMORY
-};
-
/* i386 architecture specific information. */
struct gdbarch_tdep
{
int gregset_num_regs;
size_t sizeof_gregset;
- /* The general-purpose registers used to pass integers when making
- function calls. This only applies to amd64, as all parameters
- are passed through the stack on x86. */
- int call_dummy_num_integer_regs;
- int *call_dummy_integer_regs;
-
- /* Classify TYPE according to calling conventions, and store
- the result in CLASS. Used on amd64 only. */
- void (*classify) (struct type *type, enum amd64_reg_class class[2]);
-
- /* Non-zero if the first few MEMORY arguments should be passed by
- pointer.
-
- More precisely, MEMORY arguments are passed through the stack.
- But certain architectures require that their address be passed
- by register as well, if there are still some integer registers
- available for argument passing. */
- int memory_args_by_pointer;
-
/* Floating-point registers. */
struct regset *fpregset;
size_t sizeof_fpregset;
/* Upper YMM register names. Only used for tdesc_numbered_register. */
const char **ymmh_register_names;
+ /* Register number for %bnd0r. Set this to -1 to indicate the absence
+ bound registers. */
+ int bnd0r_regnum;
+
+ /* Register number for pseudo register %bnd0. Set this to -1 to indicate the absence
+ bound registers. */
+ int bnd0_regnum;
+
+ /* Register number for %bndcfgu. Set this to -1 to indicate the absence
+ bound control registers. */
+ int bndcfgu_regnum;
+
+ /* MPX register names. Only used for tdesc_numbered_register. */
+ const char **mpx_register_names;
+
/* Target description. */
const struct target_desc *tdesc;
struct type *i386_mmx_type;
struct type *i386_ymm_type;
struct type *i387_ext_type;
+ struct type *i386_bnd_type;
/* Process record/replay target. */
/* The map for registers because the AMD64's registers order
I386_ST0_REGNUM, /* %st(0) */
I386_MXCSR_REGNUM = 40, /* %mxcsr */
I386_YMM0H_REGNUM, /* %ymm0h */
- I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7
+ I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7,
+ I386_BND0R_REGNUM,
+ I386_BND3R_REGNUM = I386_BND0R_REGNUM + 3,
+ I386_BNDCFGU_REGNUM,
+ I386_BNDSTATUS_REGNUM
};
/* Register numbers of RECORD_REGMAP. */
#define I386_SSE_NUM_REGS (I386_MXCSR_REGNUM + 1)
#define I386_AVX_NUM_REGS (I386_YMM7H_REGNUM + 1)
+#define I386_MPX_NUM_REGS (I386_BNDSTATUS_REGNUM + 1)
/* Size of the largest register. */
#define I386_MAX_REGISTER_SIZE 16
extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
+extern int i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum);
extern const char *i386_pseudo_register_name (struct gdbarch *gdbarch,
int regnum);