/* Target-dependent code for Lattice Mico32 processor, for GDB.
Contributed by Jon Beniston <jon@beniston.com>
- Copyright (C) 2009 Free Software Foundation, Inc.
+ Copyright (C) 2009-2012 Free Software Foundation, Inc.
This file is part of GDB.
struct gdbarch_tdep
{
- /* gdbarch target dependent data here. Currently unused for LM32. */
+ /* gdbarch target dependent data here. Currently unused for LM32. */
};
struct lm32_frame_cache
static struct type *
lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
{
- return builtin_type_int32;
+ return builtin_type (gdbarch)->builtin_int32;
}
/* Return non-zero if a register can't be written. */
/* Analyze a function's prologue. */
static CORE_ADDR
-lm32_analyze_prologue (CORE_ADDR pc, CORE_ADDR limit,
+lm32_analyze_prologue (struct gdbarch *gdbarch,
+ CORE_ADDR pc, CORE_ADDR limit,
struct lm32_frame_cache *info)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
unsigned long instruction;
/* Keep reading though instructions, until we come across an instruction
{
/* Read an instruction. */
- instruction = read_memory_integer (pc, 4);
+ instruction = read_memory_integer (pc, 4, byte_order);
if ((LM32_OPCODE (instruction) == OP_SW)
&& (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
{
- /* Any stack displaced store is likely part of the prologue.
+ /* Any stack displaced store is likely part of the prologue.
Record that the register is being saved, and the offset
into the stack. */
info->saved_regs[LM32_REG1 (instruction)].addr =
else if ((LM32_OPCODE (instruction) == OP_ADDI)
&& (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
{
- /* An add to the SP is likely to be part of the prologue.
+ /* An add to the SP is likely to be part of the prologue.
Adjust stack size by whatever the instruction adds to the sp. */
info->size -= LM32_IMM16 (instruction);
}
}
else
{
- /* Any other instruction is likely not to be part of the prologue. */
+ /* Any other instruction is likely not to be part of the
+ prologue. */
break;
}
}
limit_pc = pc + 100; /* Magic. */
frame_info.saved_regs = saved_regs;
- return lm32_analyze_prologue (pc, limit_pc, &frame_info);
+ return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
}
/* Create a breakpoint instruction. */
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int first_arg_reg = SIM_LM32_R1_REGNUM;
int num_arg_regs = 8;
int i;
case TYPE_CODE_ENUM:
if (TYPE_LENGTH (arg_type) < 4)
{
- arg_type = builtin_type_int32;
+ arg_type = builtin_type (gdbarch)->builtin_int32;
arg = value_cast (arg_type, arg);
}
break;
contents = (gdb_byte *) value_contents (arg);
len = TYPE_LENGTH (arg_type);
- val = extract_unsigned_integer (contents, len);
+ val = extract_unsigned_integer (contents, len, byte_order);
/* First num_arg_regs parameters are passed by registers,
and the rest are passed on the stack. */
lm32_extract_return_value (struct type *type, struct regcache *regcache,
gdb_byte *valbuf)
{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int offset;
ULONGEST l;
CORE_ADDR return_buffer;
{
/* Return value is returned in a single register. */
regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
- store_unsigned_integer (valbuf, TYPE_LENGTH (type), l);
+ store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
}
else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
{
}
else
{
- /* Aggregate types greater than a single register are returned in memory.
- FIXME: Unless they are only 2 regs?. */
+ /* Aggregate types greater than a single register are returned
+ in memory. FIXME: Unless they are only 2 regs?. */
regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
return_buffer = l;
read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
lm32_store_return_value (struct type *type, struct regcache *regcache,
const gdb_byte *valbuf)
{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST val;
int len = TYPE_LENGTH (type);
if (len <= 4)
{
- val = extract_unsigned_integer (valbuf, len);
+ val = extract_unsigned_integer (valbuf, len, byte_order);
regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
}
else if (len <= 8)
{
- val = extract_unsigned_integer (valbuf, 4);
+ val = extract_unsigned_integer (valbuf, 4, byte_order);
regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
- val = extract_unsigned_integer (valbuf + 4, len - 4);
+ val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
}
else
info->pc = get_frame_func (this_frame);
current_pc = get_frame_pc (this_frame);
- lm32_analyze_prologue (info->pc, current_pc, info);
+ lm32_analyze_prologue (get_frame_arch (this_frame),
+ info->pc, current_pc, info);
/* Compute the frame's base, and the previous frame's SP. */
this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
converted into a request for the RA register. */
info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
- /* The previous frame's SP needed to be computed. Save the computed value. */
+ /* The previous frame's SP needed to be computed. Save the computed
+ value. */
trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);
return info;
static const struct frame_unwind lm32_frame_unwind = {
NORMAL_FRAME,
+ default_frame_unwind_stop_reason,
lm32_frame_this_id,
lm32_frame_prev_register,
NULL,
return gdbarch;
}
+/* -Wmissing-prototypes */
+extern initialize_file_ftype _initialize_lm32_tdep;
+
void
_initialize_lm32_tdep (void)
{
projects / deliverable / binutils-gdb.git / blobdiff