/* Target-dependent code for Renesas M32R, for GDB.
- Copyright (C) 1996-2016 Free Software Foundation, Inc.
+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
This file is part of GDB.
#include "m32r-tdep.h"
#include <algorithm>
-/* Local functions */
+/* The size of the argument registers (r0 - r3) in bytes. */
+#define M32R_ARG_REGISTER_SIZE 4
-extern void _initialize_m32r_tdep (void);
+/* Local functions */
static CORE_ADDR
m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
return val; /* return error */
memcpy (bp_tgt->shadow_contents, contents_cache, 4);
- bp_tgt->placed_size = bp_tgt->shadow_len = 4;
+ bp_tgt->shadow_len = 4;
/* Determine appropriate breakpoint contents and size for this address. */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
return val;
}
+/* Implement the breakpoint_kind_from_pc gdbarch method. */
+
static int
m32r_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
{
return 2;
}
+/* Implement the sw_breakpoint_from_kind gdbarch method. */
+
static const gdb_byte *
m32r_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
{
}
}
-GDBARCH_BREAKPOINT_FROM_PC (m32r)
-
-char *m32r_register_names[] = {
+static const char *m32r_register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",
"psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",
m32r_store_return_value (struct type *type, struct regcache *regcache,
const gdb_byte *valbuf)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR regval;
int len = TYPE_LENGTH (type);
return info;
}
-static CORE_ADDR
-m32r_read_pc (struct regcache *regcache)
-{
- ULONGEST pc;
- regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc);
- return pc;
-}
-
static CORE_ADDR
m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
enum type_code typecode;
CORE_ADDR regval;
gdb_byte *val;
- gdb_byte valbuf[MAX_REGISTER_SIZE];
+ gdb_byte valbuf[M32R_ARG_REGISTER_SIZE];
int len;
/* First force sp to a 4-byte alignment. */
m32r_extract_return_value (struct type *type, struct regcache *regcache,
gdb_byte *dst)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int len = TYPE_LENGTH (type);
ULONGEST tmp;
return arches->gdbarch;
/* Allocate space for the new architecture. */
- tdep = XNEW (struct gdbarch_tdep);
+ tdep = XCNEW (struct gdbarch_tdep);
gdbarch = gdbarch_alloc (&info, tdep);
- set_gdbarch_read_pc (gdbarch, m32r_read_pc);
+ set_gdbarch_wchar_bit (gdbarch, 16);
+ set_gdbarch_wchar_signed (gdbarch, 0);
+
set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);
set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS);
set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
- SET_GDBARCH_BREAKPOINT_MANIPULATION (m32r);
+ set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32r_breakpoint_kind_from_pc);
+ set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32r_sw_breakpoint_from_kind);
set_gdbarch_memory_insert_breakpoint (gdbarch,
m32r_memory_insert_breakpoint);
set_gdbarch_memory_remove_breakpoint (gdbarch,
/* Return the unwound PC value. */
set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc);
- set_gdbarch_print_insn (gdbarch, print_insn_m32r);
-
/* Hook in ABI-specific overrides, if they have been registered. */
gdbarch_init_osabi (info, gdbarch);