/* Target-dependent code for Motorola 68HC11 & 68HC12
- Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
- Free Software Foundation, Inc.
+ Copyright (C) 1999-2005, 2007-2012 Free Software Foundation, Inc.
Contributed by Stephane Carrez, stcarrez@nerim.fr
MSYMBOL_IS_RTC Tests the "RTC" bit in a minimal symbol.
MSYMBOL_IS_RTI Tests the "RTC" bit in a minimal symbol. */
-#define MSYMBOL_SET_RTC(msym) \
- MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
- | 0x80000000)
+#define MSYMBOL_SET_RTC(msym) \
+ MSYMBOL_TARGET_FLAG_1 (msym) = 1
-#define MSYMBOL_SET_RTI(msym) \
- MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
- | 0x40000000)
+#define MSYMBOL_SET_RTI(msym) \
+ MSYMBOL_TARGET_FLAG_2 (msym) = 1
#define MSYMBOL_IS_RTC(msym) \
- (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
+ MSYMBOL_TARGET_FLAG_1 (msym)
#define MSYMBOL_IS_RTI(msym) \
- (((long) MSYMBOL_INFO (msym) & 0x40000000) != 0)
+ MSYMBOL_TARGET_FLAG_2 (msym)
enum insn_return_kind {
RETURN_RTS,
/* Fetch a pseudo register. The 68hc11 soft registers are treated like
pseudo registers. They are located in memory. Translate the register
fetch into a memory read. */
-static void
+static enum register_status
m68hc11_pseudo_register_read (struct gdbarch *gdbarch,
struct regcache *regcache,
int regno, gdb_byte *buf)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+
/* The PC is a pseudo reg only for 68HC12 with the memory bank
addressing mode. */
if (regno == M68HC12_HARD_PC_REGNUM)
{
ULONGEST pc;
- const int regsize = TYPE_LENGTH (builtin_type_uint32);
+ const int regsize = 4;
+ enum register_status status;
- regcache_cooked_read_unsigned (regcache, HARD_PC_REGNUM, &pc);
+ status = regcache_cooked_read_unsigned (regcache, HARD_PC_REGNUM, &pc);
+ if (status != REG_VALID)
+ return status;
if (pc >= 0x8000 && pc < 0xc000)
{
ULONGEST page;
pc += (page << 14);
pc += 0x1000000;
}
- store_unsigned_integer (buf, regsize, pc);
- return;
+ store_unsigned_integer (buf, regsize, byte_order, pc);
+ return REG_VALID;
}
m68hc11_initialize_register_info ();
{
memset (buf, 0, 2);
}
+
+ return REG_VALID;
}
/* Store a pseudo register. Translate the register store
struct regcache *regcache,
int regno, const gdb_byte *buf)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+
/* The PC is a pseudo reg only for 68HC12 with the memory bank
addressing mode. */
if (regno == M68HC12_HARD_PC_REGNUM)
{
- const int regsize = TYPE_LENGTH (builtin_type_uint32);
+ const int regsize = 4;
char *tmp = alloca (regsize);
CORE_ADDR pc;
memcpy (tmp, buf, regsize);
- pc = extract_unsigned_integer (tmp, regsize);
+ pc = extract_unsigned_integer (tmp, regsize, byte_order);
if (pc >= 0x1000000)
{
pc -= 0x1000000;
}
\f
-/* 68HC11 & 68HC12 prologue analysis.
+/* 68HC11 & 68HC12 prologue analysis. */
- */
#define MAX_CODES 12
/* 68HC11 opcodes. */
Returns a pointer to the sequence when it is recognized and
the optional value (constant/address) associated with it. */
static struct insn_sequence *
-m68hc11_analyze_instruction (struct insn_sequence *seq, CORE_ADDR pc,
+m68hc11_analyze_instruction (struct gdbarch *gdbarch,
+ struct insn_sequence *seq, CORE_ADDR pc,
CORE_ADDR *val)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
unsigned char buffer[MAX_CODES];
unsigned bufsize;
unsigned j;
if (bufsize < j + 1)
{
buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize,
- 1);
+ 1, byte_order);
bufsize++;
}
/* Continue while we match the opcode. */
}
else if ((buffer[j] & 0xfe) == 0xf0)
{
- v = read_memory_unsigned_integer (pc + j + 1, 1);
+ v = read_memory_unsigned_integer (pc + j + 1, 1, byte_order);
if (buffer[j] & 1)
v |= 0xff00;
}
else if (buffer[j] == 0xf2)
{
- v = read_memory_unsigned_integer (pc + j + 1, 2);
+ v = read_memory_unsigned_integer (pc + j + 1, 2, byte_order);
}
cur_val = v;
break;
We limit the search to 128 bytes so that the algorithm is bounded
in case of random and wrong code. We also stop and abort if
we find an instruction which is not supposed to appear in the
- prologue (as generated by gcc 2.95, 2.96).
- */
+ prologue (as generated by gcc 2.95, 2.96). */
+
func_end = pc + 128;
found_frame_point = 0;
info->size = 0;
struct insn_sequence *seq;
CORE_ADDR val;
- seq = m68hc11_analyze_instruction (seq_table, pc, &val);
+ seq = m68hc11_analyze_instruction (gdbarch, seq_table, pc, &val);
if (seq == 0)
break;
{
ULONGEST pc;
- pc = frame_unwind_register_unsigned (next_frame, gdbarch_pc_regnum (gdbarch));
+ pc = frame_unwind_register_unsigned (next_frame,
+ gdbarch_pc_regnum (gdbarch));
return pc;
}
the saved registers of frame described by FRAME_INFO. This
includes special registers such as pc and fp saved in special ways
in the stack frame. sp is even more special: the address we return
- for it IS the sp for the next frame. */
+ for it IS the sp for the next frame. */
-struct m68hc11_unwind_cache *
+static struct m68hc11_unwind_cache *
m68hc11_frame_unwind_cache (struct frame_info *this_frame,
void **this_prologue_cache)
{
}
/* Add 1 here to adjust for the post-decrement nature of the push
- instruction.*/
+ instruction. */
info->prev_sp = prev_sp;
info->base = this_base;
static const struct frame_unwind m68hc11_frame_unwind = {
NORMAL_FRAME,
+ default_frame_unwind_stop_reason,
m68hc11_frame_this_id,
m68hc11_frame_prev_register,
NULL,
V = (l & M6811_V_BIT) != 0;
C = (l & M6811_C_BIT) != 0;
- /* Print flags following the h8300 */
+ /* Print flags following the h8300. */
if ((C | Z) == 0)
fprintf_filtered (file, "u> ");
else if ((C | Z) == 1)
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int argnum;
int first_stack_argnum;
struct type *type;
{
ULONGEST v;
- v = extract_unsigned_integer (value_contents (args[0]), len);
+ v = extract_unsigned_integer (value_contents (args[0]),
+ len, byte_order);
first_stack_argnum = 1;
regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, v);
/* Store return address. */
sp -= 2;
- store_unsigned_integer (buf, 2, bp_addr);
+ store_unsigned_integer (buf, 2, byte_order, bp_addr);
write_memory (sp, buf, 2);
/* Finally, update the stack pointer... */
case HARD_A_REGNUM:
case HARD_B_REGNUM:
case HARD_CCR_REGNUM:
- return builtin_type_uint8;
+ return builtin_type (gdbarch)->builtin_uint8;
case M68HC12_HARD_PC_REGNUM:
- return builtin_type_uint32;
+ return builtin_type (gdbarch)->builtin_uint32;
default:
- return builtin_type_uint16;
+ return builtin_type (gdbarch)->builtin_uint16;
}
}
}
}
-enum return_value_convention
+static enum return_value_convention
m68hc11_return_value (struct gdbarch *gdbarch, struct type *func_type,
struct type *valtype, struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
static int
gdb_print_insn_m68hc11 (bfd_vma memaddr, disassemble_info *info)
{
- if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_m68hc11)
+ if (info->arch == bfd_arch_m68hc11)
return print_insn_m68hc11 (memaddr, info);
else
return print_insn_m68hc12 (memaddr, info);
else
elf_flags = 0;
- /* try to find a pre-existing architecture */
+ /* Try to find a pre-existing architecture. */
for (arches = gdbarch_list_lookup_by_info (arches, &info);
arches != NULL;
arches = gdbarch_list_lookup_by_info (arches->next, &info))
return arches->gdbarch;
}
- /* Need a new architecture. Fill in a target specific vector. */
+ /* Need a new architecture. Fill in a target specific vector. */
tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
gdbarch = gdbarch_alloc (&info, tdep);
tdep->elf_flags = elf_flags;
return gdbarch;
}
-extern initialize_file_ftype _initialize_m68hc11_tdep; /* -Wmissing-prototypes */
+/* -Wmissing-prototypes */
+extern initialize_file_ftype _initialize_m68hc11_tdep;
void
_initialize_m68hc11_tdep (void)
projects / deliverable / binutils-gdb.git / blobdiff