#include "frame.h"
#include "inferior.h"
#include "value.h"
-
-#ifdef USG
-#include <sys/types.h>
-#endif
-
-#include <sys/param.h>
-#include <sys/dir.h>
-#include <signal.h>
#include "gdbcore.h"
-#include <sys/user.h>
-#ifndef USER /* added to support BCS ptrace_user */
-
-#define USER ptrace_user
-#endif
-#include <sys/ioctl.h>
-#include <fcntl.h>
-
-#include <sys/file.h>
-#include <sys/stat.h>
#include "symtab.h"
#include "setjmp.h"
#include "value.h"
+/* Size of an instruction */
+#define BYTES_PER_88K_INSN 4
+
void frame_find_saved_regs ();
return 1; /* Frameless -- no saved return address */
}
-int
-frame_chain_valid (chain, thisframe)
- CORE_ADDR chain;
- struct frame_info *thisframe;
-{
- return (chain != 0
- && !inside_entry_file (FRAME_SAVED_PC (thisframe)));
-}
-
void
init_extra_frame_info (fromleaf, fi)
int fromleaf;
of the instruction. PWORD2 is ignored -- a remnant of the original
i960 version. */
-#define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
+#define NEXT_PROLOGUE_INSN(addr, lim, pword1) \
(((addr) < (lim)) ? next_insn (addr, pword1) : 0)
/* Read the m88k instruction at 'memaddr' and return the address of
{
unsigned long buf[1];
- read_memory (memaddr, buf, sizeof (buf));
- *pword1 = buf[0];
- SWAP_TARGET_AND_HOST (pword1, sizeof (long));
-
- return memaddr + 4;
+ *pword1 = read_memory_integer (memaddr, BYTES_PER_88K_INSN);
+ return memaddr + BYTES_PER_88K_INSN;
}
/* Read a register from frames called by us (or from the hardware regs). */
-int
+static int
read_next_frame_reg(fi, regno)
FRAME fi;
int regno;
register CORE_ADDR next_ip;
register int src;
register struct pic_prologue_code *pcode;
- unsigned int insn1, insn2;
+ unsigned int insn;
int size, offset;
char must_adjust[32]; /* If set, must adjust offsets in fsr */
int sp_offset = -1; /* -1 means not set (valid must be mult of 8) */
int fp_offset = -1; /* -1 means not set */
CORE_ADDR frame_fp;
- bzero (must_adjust, sizeof (must_adjust));
- next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2);
+ memset (must_adjust, '\0', sizeof (must_adjust));
+ next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn);
/* Accept move of incoming registers to other registers, using
"or rd,rs,0" or "or.u rd,rs,0" or "or rd,r0,rs" or "or rd,rs,r0".
#define OR_REG_MOVE2_INSN 0xF4005800 /* or rd,rs,r0 */
#define OR_REG_MOVE2_MASK 0xFC00FFFF
while (next_ip &&
- ((insn1 & OR_MOVE_MASK) == OR_MOVE_INSN ||
- (insn1 & OR_REG_MOVE1_MASK) == OR_REG_MOVE1_INSN ||
- (insn1 & OR_REG_MOVE2_MASK) == OR_REG_MOVE2_INSN
+ ((insn & OR_MOVE_MASK) == OR_MOVE_INSN ||
+ (insn & OR_REG_MOVE1_MASK) == OR_REG_MOVE1_INSN ||
+ (insn & OR_REG_MOVE2_MASK) == OR_REG_MOVE2_INSN
)
)
{
has already been reflected in what the compiler tells us is the
location of these parameters. */
ip = next_ip;
- next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2);
+ next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn);
}
/* Accept an optional "subu sp,sp,n" to set up the stack pointer. */
#define SUBU_SP_MASK 0xffff0007 /* Note offset must be mult. of 8 */
#define SUBU_OFFSET(x) ((unsigned)(x & 0xFFFF))
if (next_ip &&
- ((insn1 & SUBU_SP_MASK) == SUBU_SP_INSN)) /* subu r31, r31, N */
+ ((insn & SUBU_SP_MASK) == SUBU_SP_INSN)) /* subu r31, r31, N */
{
- sp_offset = -SUBU_OFFSET (insn1);
+ sp_offset = -SUBU_OFFSET (insn);
ip = next_ip;
- next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2);
+ next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn);
}
/* The function must start with a stack-pointer adjustment, or
while (next_ip)
{
- if ((insn1 & ST_STACK_MASK) == ST_STACK_INSN)
+ if ((insn & ST_STACK_MASK) == ST_STACK_INSN)
size = 1;
- else if ((insn1 & STD_STACK_MASK) == STD_STACK_INSN)
+ else if ((insn & STD_STACK_MASK) == STD_STACK_INSN)
size = 2;
else
break;
- src = ST_SRC (insn1);
- offset = ST_OFFSET (insn1);
+ src = ST_SRC (insn);
+ offset = ST_OFFSET (insn);
while (size--)
{
must_adjust[src] = 1;
offset += 4;
}
ip = next_ip;
- next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2);
+ next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn);
}
/* Accept an optional "addu r30,r31,n" to set up the frame pointer. */
#define ADDU_FP_MASK 0xffff0000
#define ADDU_OFFSET(x) ((unsigned)(x & 0xFFFF))
if (next_ip &&
- ((insn1 & ADDU_FP_MASK) == ADDU_FP_INSN)) /* addu r30, r31, N */
+ ((insn & ADDU_FP_MASK) == ADDU_FP_INSN)) /* addu r30, r31, N */
{
- fp_offset = ADDU_OFFSET (insn1);
+ fp_offset = ADDU_OFFSET (insn);
ip = next_ip;
- next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2);
+ next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn);
}
/* Accept the PIC prologue code if present. */
size-=2;
}
- while (size-- && next_ip && (pcode->insn == (pcode->mask & insn1)))
+ while (size-- && next_ip && (pcode->insn == (pcode->mask & insn)))
{
pcode++;
ip = next_ip;
- next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2);
+ next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn);
}
/* Accept moves of parameter registers to other registers, using
#define OR_REG_MOVE2_INSN 0xF4005800 /* or rd,rs,r0 */
#define OR_REG_MOVE2_MASK 0xFC00FFFF
while (next_ip &&
- ((insn1 & OR_MOVE_MASK) == OR_MOVE_INSN ||
- (insn1 & OR_REG_MOVE1_MASK) == OR_REG_MOVE1_INSN ||
- (insn1 & OR_REG_MOVE2_MASK) == OR_REG_MOVE2_INSN
+ ((insn & OR_MOVE_MASK) == OR_MOVE_INSN ||
+ (insn & OR_REG_MOVE1_MASK) == OR_REG_MOVE1_INSN ||
+ (insn & OR_REG_MOVE2_MASK) == OR_REG_MOVE2_INSN
)
)
{
has already been reflected in what the compiler tells us is the
location of these parameters. */
ip = next_ip;
- next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2);
+ next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn);
}
/* We're done with the prologue. If we don't care about the stack
if (fi == 0)
return ip;
- /* OK, now we have:
- sp_offset original negative displacement of SP
- fp_offset positive displacement between new SP and new FP, or -1
- fsr->regs[0..31] offset from original SP where reg is stored
- must_adjust[0..31] set if corresp. offset was set
+ /*
+ OK, now we have:
+
+ sp_offset original (before any alloca calls) displacement of SP
+ (will be negative).
+
+ fp_offset displacement from original SP to the FP for this frame
+ or -1.
+
+ fsr->regs[0..31] displacement from original SP to the stack
+ location where reg[0..31] is stored.
- The current SP (frame_sp) might not be the original new SP as set
- by the function prologue, if alloca has been called. This can
- only occur if fp_offset is set, though (the compiler allocates an
- FP when it sees alloca). In that case, we have the FP,
- and can calculate the original new SP from the FP.
+ must_adjust[0..31] set if corresponding offset was set.
- Then, we figure out where the arguments and locals are, and
- relocate the offsets in fsr->regs to absolute addresses. */
+ If alloca has been called between the function prologue and the current
+ IP, then the current SP (frame_sp) will not be the original SP as set by
+ the function prologue. If the current SP is not the original SP, then the
+ compiler will have allocated an FP for this frame, fp_offset will be set,
+ and we can use it to calculate the original SP.
+
+ Then, we figure out where the arguments and locals are, and relocate the
+ offsets in fsr->regs to absolute addresses. */
if (fp_offset != -1) {
/* We have a frame pointer, so get it, and base our calc's on it. */
- frame_fp = (CORE_ADDR) read_next_frame_reg (fi->next, FP_REGNUM);
+ frame_fp = (CORE_ADDR) read_next_frame_reg (fi->next, ACTUAL_FP_REGNUM);
frame_sp = frame_fp - fp_offset;
} else {
/* We have no frame pointer, therefore frame_sp is still the same value
cache_fsr = (struct frame_saved_regs *)
obstack_alloc (&frame_cache_obstack,
sizeof (struct frame_saved_regs));
- bzero (cache_fsr, sizeof (struct frame_saved_regs));
+ memset (cache_fsr, '\0', sizeof (struct frame_saved_regs));
fi->fsr = cache_fsr;
/* Find the start and end of the function prologue. If the PC
}
-#if TARGET_BYTE_ORDER != HOST_BYTE_ORDER
-you lose
-#else /* Host and target byte order the same. */
-#define SINGLE_EXP_BITS 8
-#define DOUBLE_EXP_BITS 11
-int
-IEEE_isNAN(fp, len)
- int *fp, len;
- /* fp points to a single precision OR double precision
- * floating point value; len is the number of bytes, either 4 or 8.
- * Returns 1 iff fp points to a valid IEEE floating point number.
- * Returns 0 if fp points to a denormalized number or a NaN
- */
-{
- int exponent;
- if (len == 4)
- {
- exponent = *fp;
- exponent = exponent << 1 >> (32 - SINGLE_EXP_BITS - 1);
- return ((exponent == -1) || (! exponent && *fp));
- }
- else if (len == 8)
- {
- exponent = *(fp+1);
- exponent = exponent << 1 >> (32 - DOUBLE_EXP_BITS - 1);
- return ((exponent == -1) || (! exponent && *fp * *(fp+1)));
- }
- else return 1;
-}
-#endif /* Host and target byte order the same. */
-
static int
pushed_size (prev_words, v)
int prev_words;
case TYPE_CODE_ENUM: /* Enumeration type */
case TYPE_CODE_INT: /* Integer type */
case TYPE_CODE_REF: /* C++ Reference types */
- case TYPE_CODE_ARRAY: /* Array type, lower bound zero */
+ case TYPE_CODE_ARRAY: /* Array type, lower & upper bounds */
return 1;
case TYPE_CODE_FUNC: /* Function type */
case TYPE_CODE_SET: /* Pascal sets */
case TYPE_CODE_RANGE: /* Range (integers within bounds) */
- case TYPE_CODE_PASCAL_ARRAY: /* Array with explicit type of index */
+ case TYPE_CODE_STRING: /* String type */
case TYPE_CODE_MEMBER: /* Member type */
case TYPE_CODE_METHOD: /* Method type */
/* Don't know how to pass these yet. */
CORE_ADDR address;
int val;
{
- write_memory (address, &val, 4);
+ write_memory (address, (char *)&val, 4);
}
static int
case TYPE_CODE_PTR: /* Pointer type */
case TYPE_CODE_ENUM: /* Enumeration type */
case TYPE_CODE_INT: /* Integer type */
- case TYPE_CODE_ARRAY: /* Array type, lower bound zero */
+ case TYPE_CODE_ARRAY: /* Array type, lower & upper bounds */
case TYPE_CODE_REF: /* C++ Reference types */
store_parm_word (start, *val_addr);
{
char retbuf[REGISTER_BYTES];
- bcopy (registers, retbuf, REGISTER_BYTES);
+ memcpy (retbuf, registers, REGISTER_BYTES);
*rval = value_being_returned (value_type, retbuf, struct_return);
return;
}
projects / deliverable / binutils-gdb.git / blobdiff