#include "opcode/mips.h"
#include "elf/mips.h"
#include "elf-bfd.h"
-
+#include "symcat.h"
/* The sizes of floating point registers. */
#define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
#endif
+static int mips_debug = 0;
/* MIPS specific per-architecture information */
struct gdbarch_tdep
int mips_fp_register_double;
int mips_regs_have_home_p;
int mips_default_stack_argsize;
+ int gdb_target_is_mips64;
};
#if GDB_MULTI_ARCH
return 4;
}
-
+#if GDB_MULTI_ARCH
+#undef GDB_TARGET_IS_MIPS64
+#define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
+#endif
#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
mips_addr_bits_remove (addr)
CORE_ADDR addr;
{
-#if GDB_TARGET_IS_MIPS64
- if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
+ if (GDB_TARGET_IS_MIPS64)
{
- /* This hack is a work-around for existing boards using PMON,
- the simulator, and any other 64-bit targets that doesn't have
- true 64-bit addressing. On these targets, the upper 32 bits
- of addresses are ignored by the hardware. Thus, the PC or SP
- are likely to have been sign extended to all 1s by instruction
- sequences that load 32-bit addresses. For example, a typical
- piece of code that loads an address is this:
- lui $r2, <upper 16 bits>
- ori $r2, <lower 16 bits>
- But the lui sign-extends the value such that the upper 32 bits
- may be all 1s. The workaround is simply to mask off these bits.
- In the future, gcc may be changed to support true 64-bit
- addressing, and this masking will have to be disabled. */
+ if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
+ {
+ /* This hack is a work-around for existing boards using
+ PMON, the simulator, and any other 64-bit targets that
+ doesn't have true 64-bit addressing. On these targets,
+ the upper 32 bits of addresses are ignored by the
+ hardware. Thus, the PC or SP are likely to have been
+ sign extended to all 1s by instruction sequences that
+ load 32-bit addresses. For example, a typical piece of
+ code that loads an address is this: lui $r2, <upper 16
+ bits> ori $r2, <lower 16 bits> But the lui sign-extends
+ the value such that the upper 32 bits may be all 1s. The
+ workaround is simply to mask off these bits. In the
+ future, gcc may be changed to support true 64-bit
+ addressing, and this masking will have to be disabled. */
+ addr &= (CORE_ADDR) 0xffffffff;
+ }
+ }
+ else
+ {
+ /* Even when GDB is configured for some 32-bit targets
+ (e.g. mips-elf), BFD is configured to handle 64-bit targets,
+ so CORE_ADDR is 64 bits. So we still have to mask off
+ useless bits from addresses. */
addr &= (CORE_ADDR) 0xffffffff;
}
-#else
- /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
- BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
- So we still have to mask off useless bits from addresses. */
- addr &= (CORE_ADDR) 0xffffffff;
-#endif
-
return addr;
}
return create_new_frame (argv[0], argv[1]);
}
+/* According to the current ABI, should the type be passed in a
+ floating-point register (assuming that there is space)? When there
+ is no FPU, FP are not even considered as possibile candidates for
+ FP registers and, consequently this returns false - forces FP
+ arguments into integer registers. */
+
+static int
+fp_register_arg_p (enum type_code typecode, struct type *arg_type)
+{
+ return ((typecode == TYPE_CODE_FLT
+ || (MIPS_EABI
+ && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
+ && TYPE_NFIELDS (arg_type) == 1
+ && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
+ && MIPS_FPU_TYPE != MIPS_FPU_NONE);
+}
+
CORE_ADDR
mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
int nargs;
len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_SAVED_REGSIZE);
sp -= ROUND_UP (len, 16);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n",
+ (long) sp, ROUND_UP (len, 16));
+
/* Initialize the integer and float register pointers. */
argreg = A0_REGNUM;
float_argreg = FPA0_REGNUM;
/* the struct_return pointer occupies the first parameter-passing reg */
if (struct_return)
- write_register (argreg++, struct_addr);
+ {
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog,
+ "mips_push_arguments: struct_return at r%d 0x%lx\n",
+ argreg, (long) struct_addr);
+ write_register (argreg++, struct_addr);
+ }
/* Now load as many as possible of the first arguments into
registers, and push the rest onto the stack. Loop thru args
int len = TYPE_LENGTH (arg_type);
enum type_code typecode = TYPE_CODE (arg_type);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog,
+ "mips_push_arguments: %d len=%d type=%d",
+ argnum, len, (int) typecode);
+
/* The EABI passes structures that do not fit in a register by
reference. In all other cases, pass the structure by value. */
- if (MIPS_EABI && len > MIPS_SAVED_REGSIZE &&
- (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
+ if (MIPS_EABI
+ && len > MIPS_SAVED_REGSIZE
+ && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
{
store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
typecode = TYPE_CODE_PTR;
len = MIPS_SAVED_REGSIZE;
val = valbuf;
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " push");
}
else
val = (char *) VALUE_CONTENTS (arg);
don't use float registers for arguments. This duplication of
arguments in general registers can't hurt non-MIPS16 functions
because those registers are normally skipped. */
- if (typecode == TYPE_CODE_FLT
- && float_argreg <= MIPS_LAST_FP_ARG_REGNUM
- && MIPS_FPU_TYPE != MIPS_FPU_NONE)
+ /* MIPS_EABI squeeses a struct that contains a single floating
+ point value into an FP register instead of pusing it onto the
+ stack. */
+ if (fp_register_arg_p (typecode, arg_type)
+ && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
{
if (!FP_REGISTER_DOUBLE && len == 8)
{
/* Write the low word of the double to the even register(s). */
regval = extract_unsigned_integer (val + low_offset, 4);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " fpreg=%d val=%s",
+ float_argreg, phex (regval, 4));
write_register (float_argreg++, regval);
if (!MIPS_EABI)
- write_register (argreg + 1, regval);
+ {
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " reg=%d val=%s",
+ argreg, phex (regval, 4));
+ write_register (argreg++, regval);
+ }
/* Write the high word of the double to the odd register(s). */
regval = extract_unsigned_integer (val + 4 - low_offset, 4);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " fpreg=%d val=%s",
+ float_argreg, phex (regval, 4));
write_register (float_argreg++, regval);
if (!MIPS_EABI)
{
- write_register (argreg, regval);
- argreg += 2;
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " reg=%d val=%s",
+ argreg, phex (regval, 4));
+ write_register (argreg++, regval);
}
}
in a single register. */
/* On 32 bit ABI's the float_argreg is further adjusted
above to ensure that it is even register aligned. */
- CORE_ADDR regval = extract_address (val, len);
+ LONGEST regval = extract_unsigned_integer (val, len);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " fpreg=%d val=%s",
+ float_argreg, phex (regval, len));
write_register (float_argreg++, regval);
if (!MIPS_EABI)
{
registers for each argument. The below is (my
guess) to ensure that the corresponding integer
register has reserved the same space. */
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, " reg=%d val=%s",
+ argreg, phex (regval, len));
write_register (argreg, regval);
argreg += FP_REGISTER_DOUBLE ? 1 : 2;
}
are treated specially: Irix cc passes them in registers
where gcc sometimes puts them on the stack. For maximum
compatibility, we will put them in both places. */
-
int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
(len % MIPS_SAVED_REGSIZE != 0));
+ /* Note: Floating-point values that didn't fit into an FP
+ register are only written to memory. */
while (len > 0)
{
+ /* Rememer if the argument was written to the stack. */
+ int stack_used_p = 0;
int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
- if (argreg > MIPS_LAST_ARG_REGNUM || odd_sized_struct)
+ /* Write this portion of the argument to the stack. */
+ if (argreg > MIPS_LAST_ARG_REGNUM
+ || odd_sized_struct
+ || fp_register_arg_p (typecode, arg_type))
{
- /* Write this portion of the argument to the stack. */
/* Should shorter than int integer values be
promoted to int before being stored? */
-
int longword_offset = 0;
+ CORE_ADDR addr;
+ stack_used_p = 1;
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
{
if (MIPS_STACK_ARGSIZE == 8 &&
longword_offset = MIPS_STACK_ARGSIZE - len;
}
- write_memory (sp + stack_offset + longword_offset,
- val, partial_len);
+ if (mips_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, " stack_offset=0x%lx",
+ (long) stack_offset);
+ fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx",
+ (long) longword_offset);
+ }
+
+ addr = sp + stack_offset + longword_offset;
+
+ if (mips_debug)
+ {
+ int i;
+ fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr);
+ for (i = 0; i < partial_len; i++)
+ {
+ fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff);
+ }
+ }
+ write_memory (addr, val, partial_len);
}
- /* Note!!! This is NOT an else clause.
- Odd sized structs may go thru BOTH paths. */
- if (argreg <= MIPS_LAST_ARG_REGNUM)
+ /* Note!!! This is NOT an else clause. Odd sized
+ structs may go thru BOTH paths. Floating point
+ arguments will not. */
+ /* Write this portion of the argument to a general
+ purpose register. */
+ if (argreg <= MIPS_LAST_ARG_REGNUM
+ && !fp_register_arg_p (typecode, arg_type))
{
- CORE_ADDR regval = extract_address (val, partial_len);
+ LONGEST regval = extract_unsigned_integer (val, partial_len);
/* A non-floating-point argument being passed in a
general register. If a struct or union, and if
regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
TARGET_CHAR_BIT);
+ if (mips_debug)
+ fprintf_filtered (gdb_stdlog, " reg=%d val=%s",
+ argreg,
+ phex (regval, MIPS_SAVED_REGSIZE));
write_register (argreg, regval);
argreg++;
len -= partial_len;
val += partial_len;
- /* The offset onto the stack at which we will start
- copying parameters (after the registers are used up)
- begins at (4 * MIPS_REGSIZE) in the old ABI. This
- leaves room for the "home" area for register parameters.
+ /* Compute the the offset into the stack at which we
+ will copy the next parameter.
+
+ In older ABIs, the caller reserved space for
+ registers that contained arguments. This was loosely
+ refered to as their "home". Consequently, space is
+ always allocated.
- In the new EABI (and the NABI32), the 8 register parameters
- do not have "home" stack space reserved for them, so the
- stack offset does not get incremented until after
- we have used up the 8 parameter registers. */
+ In the new EABI (and the NABI32), the stack_offset
+ only needs to be adjusted when it has been used.. */
- if (MIPS_REGS_HAVE_HOME_P || argnum >= 8)
+ if (MIPS_REGS_HAVE_HOME_P || stack_used_p)
stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
}
}
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stdlog, "\n");
}
/* Return adjusted stack pointer. */
This is a helper function for mips_skip_prologue. */
static CORE_ADDR
-mips32_skip_prologue (pc, lenient)
- CORE_ADDR pc; /* starting PC to search from */
- int lenient;
+mips32_skip_prologue (CORE_ADDR pc)
{
t_inst inst;
CORE_ADDR end_pc;
This is a helper function for mips_skip_prologue. */
static CORE_ADDR
-mips16_skip_prologue (pc, lenient)
- CORE_ADDR pc; /* starting PC to search from */
- int lenient;
+mips16_skip_prologue (CORE_ADDR pc)
{
CORE_ADDR end_pc;
int extend_bytes = 0;
delay slot of a non-prologue instruction). */
CORE_ADDR
-mips_skip_prologue (pc, lenient)
- CORE_ADDR pc;
- int lenient;
+mips_skip_prologue (CORE_ADDR pc)
{
/* See if we can determine the end of the prologue via the symbol table.
If so, then return either PC, or the PC after the prologue, whichever
instructions. */
if (pc_is_mips16 (pc))
- return mips16_skip_prologue (pc, lenient);
+ return mips16_skip_prologue (pc);
else
- return mips32_skip_prologue (pc, lenient);
+ return mips32_skip_prologue (pc);
}
-#if 0
-/* The lenient prologue stuff should be superseded by the code in
- init_extra_frame_info which looks to see whether the stores mentioned
- in the proc_desc have actually taken place. */
-
-/* Is address PC in the prologue (loosely defined) for function at
- STARTADDR? */
-
-static int
-mips_in_lenient_prologue (startaddr, pc)
- CORE_ADDR startaddr;
- CORE_ADDR pc;
-{
- CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1);
- return pc >= startaddr && pc < end_prologue;
-}
-#endif
-
/* Determine how a return value is stored within the MIPS register
file, given the return type `valtype'. */
it's definitely a 16-bit function. Otherwise, we have to just
guess that if the address passed in is odd, it's 16-bits. */
if (proc_desc)
- info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : TM_PRINT_INSN_MACH;
+ info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
+ bfd_mach_mips16 : TM_PRINT_INSN_MACH;
else
- info->mach = pc_is_mips16 (memaddr) ? 16 : TM_PRINT_INSN_MACH;
+ info->mach = pc_is_mips16 (memaddr) ?
+ bfd_mach_mips16 : TM_PRINT_INSN_MACH;
/* Round down the instruction address to the appropriate boundary. */
- memaddr &= (info->mach == 16 ? ~1 : ~3);
+ memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
/* Call the appropriate disassembler based on the target endian-ness. */
if (TARGET_BYTE_ORDER == BIG_ENDIAN)
*addrp = addr;
}
+/* Immediately after a function call, return the saved pc.
+ Can't always go through the frames for this because on some machines
+ the new frame is not set up until the new function executes
+ some instructions. */
+
+static CORE_ADDR
+mips_saved_pc_after_call (struct frame_info *frame)
+{
+
+ return read_register (RA_REGNUM);
+}
+
+
static gdbarch_init_ftype mips_gdbarch_init;
static struct gdbarch *
mips_gdbarch_init (info, arches)
struct gdbarch *gdbarch;
struct gdbarch_tdep *tdep;
int elf_flags;
+#if 0
int ef_mips_bitptrs;
+#endif
+#if 0
int ef_mips_arch;
+#endif
enum mips_abi mips_abi;
/* Extract the elf_flags if available */
mips_abi = MIPS_ABI_EABI32;
break;
case E_MIPS_ABI_EABI64:
- mips_abi = MIPS_ABI_EABI32;
+ mips_abi = MIPS_ABI_EABI64;
break;
default:
mips_abi = MIPS_ABI_UNKNOWN;
if (gdbarch_debug)
{
fprintf_unfiltered (gdb_stdlog,
- "mips_gdbarch_init: elf_flags = %08x\n",
+ "mips_gdbarch_init: elf_flags = 0x%08x\n",
elf_flags);
+#if 0
fprintf_unfiltered (gdb_stdlog,
"mips_gdbarch_init: ef_mips_arch = %d\n",
ef_mips_arch);
+#endif
+#if 0
fprintf_unfiltered (gdb_stdlog,
"mips_gdbarch_init: ef_mips_bitptrs = %d\n",
ef_mips_bitptrs);
+#endif
fprintf_unfiltered (gdb_stdlog,
"mips_gdbarch_init: mips_abi = %d\n",
mips_abi);
tdep->mips_last_arg_regnum = ZERO_REGNUM + 7;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
tdep->mips_regs_have_home_p = 1;
+ tdep->gdb_target_is_mips64 = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
tdep->mips_last_arg_regnum = ZERO_REGNUM + 7;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
tdep->mips_regs_have_home_p = 1;
+ tdep->gdb_target_is_mips64 = 1;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
+ tdep->gdb_target_is_mips64 = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
+ tdep->gdb_target_is_mips64 = 1;
set_gdbarch_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
set_gdbarch_long_long_bit (gdbarch, 64);
tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
+ tdep->gdb_target_is_mips64 = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 1;
+ tdep->gdb_target_is_mips64 = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
the current gcc - it would make GDB treat these 64-bit programs
as 32-bit programs by default. */
+#if 0
/* determine the ISA */
switch (elf_flags & EF_MIPS_ARCH)
{
default:
break;
}
+#endif
#if 0
/* determine the size of a pointer */
set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+ set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
+ set_gdbarch_decr_pc_after_break (gdbarch, 0);
+ set_gdbarch_ieee_float (gdbarch, 1);
+
+ set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
+ set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
+
return gdbarch;
}
fprintf_unfiltered (file,
"mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d\n",
MIPS_LAST_FP_ARG_REGNUM);
- fprintf_unfiltered (file,
- "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d\n",
- MIPS_LAST_ARG_REGNUM);
fprintf_unfiltered (file,
"mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
MIPS_FPU_TYPE,
fprintf_unfiltered (file,
"mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
MIPS_DEFAULT_SAVED_REGSIZE);
- fprintf_unfiltered (file,
- "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
- MIPS_SAVED_REGSIZE);
fprintf_unfiltered (file,
"mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
FP_REGISTER_DOUBLE);
fprintf_unfiltered (file,
"mips_dump_tdep: MIPS_REGSIZE = %d\n",
MIPS_REGSIZE);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: A0_REGNUM = %d\n",
+ A0_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
+ XSTRING (ADDR_BITS_REMOVE(ADDR)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: ATTACH_DETACH # %s\n",
+ XSTRING (ATTACH_DETACH));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
+ BADVADDR_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: CAUSE_REGNUM = %d\n",
+ CAUSE_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: CPLUS_MARKER = %c\n",
+ CPLUS_MARKER);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
+ DEFAULT_MIPS_TYPE);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
+ XSTRING (DO_REGISTERS_INFO));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
+ XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
+ XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
+ XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: FCRCS_REGNUM = %d\n",
+ FCRCS_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: FCRIR_REGNUM = %d\n",
+ FCRIR_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
+ FIRST_EMBED_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: FPA0_REGNUM = %d\n",
+ FPA0_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
+ GDB_TARGET_IS_MIPS64);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
+ XSTRING (GDB_TARGET_MASK_DISAS_PC (PC)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
+ XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
+ GEN_REG_SAVE_MASK);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
+ XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: HI_REGNUM = %d\n",
+ HI_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
+ XSTRING (IGNORE_HELPER_CALL (PC)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: INIT_FRAME_PC # %s\n",
+ XSTRING (INIT_FRAME_PC (FROMLEAF, PREV)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n",
+ XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF, PREV)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: IN_SIGTRAMP # %s\n",
+ XSTRING (IN_SIGTRAMP (PC, NAME)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
+ XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
+ XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
+ LAST_EMBED_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: LO_REGNUM = %d\n",
+ LO_REGNUM);
+#ifdef MACHINE_CPROC_FP_OFFSET
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
+ MACHINE_CPROC_FP_OFFSET);
+#endif
+#ifdef MACHINE_CPROC_PC_OFFSET
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
+ MACHINE_CPROC_PC_OFFSET);
+#endif
+#ifdef MACHINE_CPROC_SP_OFFSET
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
+ MACHINE_CPROC_SP_OFFSET);
+#endif
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
+ MIPS16_INSTLEN);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS_INSTLEN = %d\n",
+ MIPS_INSTLEN);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d\n",
+ MIPS_LAST_ARG_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS_NUMREGS = %d\n",
+ MIPS_NUMREGS);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
+ MIPS_SAVED_REGSIZE);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
+ XSTRING (MSYMBOL_SIZE (MSYM)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: OP_LDFPR = used?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: OP_LDGPR = used?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PRID_REGNUM = %d\n",
+ PRID_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
+ XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_FRAME_REG = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_FREG_MASK = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_PC_REG = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_REG_MASK = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PROC_SYMBOL = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PS_REGNUM = %d\n",
+ PS_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
+ PUSH_FP_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: RA_REGNUM = %d\n",
+ RA_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
+ XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
+ XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: REGISTER_NAMES = delete?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: ROUND_DOWN = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: ROUND_UP = function?\n");
+#ifdef SAVED_BYTES
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SAVED_BYTES = %d\n",
+ SAVED_BYTES);
+#endif
+#ifdef SAVED_FP
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SAVED_FP = %d\n",
+ SAVED_FP);
+#endif
+#ifdef SAVED_PC
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SAVED_PC = %d\n",
+ SAVED_PC);
+#endif
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
+ XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SIGFRAME_BASE = %d\n",
+ SIGFRAME_BASE);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
+ SIGFRAME_FPREGSAVE_OFF);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
+ SIGFRAME_PC_OFF);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
+ SIGFRAME_REGSAVE_OFF);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
+ SIGFRAME_REG_SIZE);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
+ XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
+ XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
+ SOFTWARE_SINGLE_STEP_P);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
+ SOFTWARE_SINGLE_STEP_P);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
+ XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
+#ifdef STACK_END_ADDR
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: STACK_END_ADDR = %d\n",
+ STACK_END_ADDR);
+#endif
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
+ XSTRING (STEP_SKIPS_DELAY (PC)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
+ STEP_SKIPS_DELAY_P);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
+ XSTRING (STOPPED_BY_WATCHPOINT (WS)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: T9_REGNUM = %d\n",
+ T9_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
+ XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
+ XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TARGET_MIPS = used?\n");
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
+ XSTRING (TM_PRINT_INSN_MACH));
+#ifdef TRACE_CLEAR
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TRACE_CLEAR # %s\n",
+ XSTRING (TRACE_CLEAR (THREAD, STATE)));
+#endif
+#ifdef TRACE_FLAVOR
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TRACE_FLAVOR = %d\n",
+ TRACE_FLAVOR);
+#endif
+#ifdef TRACE_FLAVOR_SIZE
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
+ TRACE_FLAVOR_SIZE);
+#endif
+#ifdef TRACE_SET
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: TRACE_SET # %s\n",
+ XSTRING (TRACE_SET (X,STATE)));
+#endif
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
+#ifdef UNUSED_REGNUM
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: UNUSED_REGNUM = %d\n",
+ UNUSED_REGNUM);
+#endif
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: V0_REGNUM = %d\n",
+ V0_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
+ (long) VM_MIN_ADDRESS);
+#ifdef VX_NUM_REGS
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
+ VX_NUM_REGS);
+#endif
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: ZERO_REGNUM = %d\n",
+ ZERO_REGNUM);
+ fprintf_unfiltered (file,
+ "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
+ _PROC_MAGIC_);
}
void
64 bits for others. Use \"off\" to disable compatibility mode",
&setlist),
&showlist);
+
+ /* Debug this files internals. */
+ add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
+ &mips_debug, "Set mips debugging.\n\
+When non-zero, mips specific debugging is enabled.", &setdebuglist),
+ &showdebuglist);
}
+
projects / deliverable / binutils-gdb.git / blobdiff