/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
- Copyright (C) 1988-2014 Free Software Foundation, Inc.
+ Copyright (C) 1988-2016 Free Software Foundation, Inc.
Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
CORE_ADDR addr, int mustbe32);
+static void mips_print_float_info (struct gdbarch *, struct ui_file *,
+ struct frame_info *, const char *);
+
/* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
#define ST0_FR (1 << 26)
if (ELF_ST_IS_MICROMIPS (st_other))
{
- MSYMBOL_TARGET_FLAG_2 (msym) = 1;
+ MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1;
SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
}
else if (ELF_ST_IS_MIPS16 (st_other))
{
- MSYMBOL_TARGET_FLAG_1 (msym) = 1;
+ MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1;
SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
}
}
static int
msymbol_is_mips (struct minimal_symbol *msym)
{
- return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym));
+ return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym)
+ | MSYMBOL_TARGET_FLAG_MICROMIPS (msym));
}
/* Return one iff MSYM refers to MIPS16 code. */
static int
msymbol_is_mips16 (struct minimal_symbol *msym)
{
- return MSYMBOL_TARGET_FLAG_1 (msym);
+ return MSYMBOL_TARGET_FLAG_MIPS16 (msym);
}
/* Return one iff MSYM refers to microMIPS code. */
static int
msymbol_is_micromips (struct minimal_symbol *msym)
{
- return MSYMBOL_TARGET_FLAG_2 (msym);
+ return MSYMBOL_TARGET_FLAG_MICROMIPS (msym);
}
/* Set the ISA bit in the main symbol too, complementing the corresponding
return 0;
/* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
- if (strncmp (name, mips_str_mips16_call_stub,
- strlen (mips_str_mips16_call_stub)) == 0)
+ if (startswith (name, mips_str_mips16_call_stub))
return 1;
/* If the PC is in __call_stub_*, this is a call/return or a call stub. */
- if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0)
+ if (startswith (name, mips_str_call_stub))
return 1;
/* If the PC is in __fn_stub_*, this is a call stub. */
- if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0)
+ if (startswith (name, mips_str_fn_stub))
return 1;
return 0; /* Not a stub. */
static ULONGEST
mips_fetch_instruction (struct gdbarch *gdbarch,
- enum mips_isa isa, CORE_ADDR addr, int *statusp)
+ enum mips_isa isa, CORE_ADDR addr, int *errp)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[MIPS_INSN32_SIZE];
int instlen;
- int status;
+ int err;
switch (isa)
{
internal_error (__FILE__, __LINE__, _("invalid ISA"));
break;
}
- status = target_read_memory (addr, buf, instlen);
- if (statusp != NULL)
- *statusp = status;
- if (status)
+ err = target_read_memory (addr, buf, instlen);
+ if (errp != NULL)
+ *errp = err;
+ if (err != 0)
{
- if (statusp == NULL)
- memory_error (status, addr);
+ if (errp == NULL)
+ memory_error (TARGET_XFER_E_IO, addr);
return 0;
}
return extract_unsigned_integer (buf, instlen, byte_order);
switch (isa)
{
case ISA_MICROMIPS:
- if (micromips_op (insn) == 0x1f)
- return 3 * MIPS_INSN16_SIZE;
- else if (((micromips_op (insn) & 0x4) == 0x4)
- || ((micromips_op (insn) & 0x7) == 0x0))
+ if ((micromips_op (insn) & 0x4) == 0x4
+ || (micromips_op (insn) & 0x7) == 0x0)
return 2 * MIPS_INSN16_SIZE;
else
return MIPS_INSN16_SIZE;
pc += MIPS_INSN16_SIZE;
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
- /* 48-bit instructions. */
- case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
- /* No branch or jump instructions in this category. */
- pc += 2 * MIPS_INSN16_SIZE;
- break;
-
/* 32-bit instructions. */
case 2 * MIPS_INSN16_SIZE:
insn <<= 16;
struct mips_frame_cache *cache;
if ((*this_cache) != NULL)
- return (*this_cache);
+ return (struct mips_frame_cache *) (*this_cache);
cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
(*this_cache) = cache;
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
if (start_addr == 0)
return cache;
- mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
+ mips16_scan_prologue (gdbarch, start_addr, pc, this_frame,
+ (struct mips_frame_cache *) *this_cache);
}
/* gdbarch_sp_regnum contains the value and not the address. */
gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
cache->base);
- return (*this_cache);
+ return (struct mips_frame_cache *) (*this_cache);
}
static void
loc += MIPS_INSN16_SIZE;
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
- /* 48-bit instructions. */
- case 3 * MIPS_INSN16_SIZE:
- /* No prologue instructions in this category. */
- this_non_prologue_insn = 1;
- loc += 2 * MIPS_INSN16_SIZE;
- break;
-
/* 32-bit instructions. */
case 2 * MIPS_INSN16_SIZE:
insn <<= 16;
struct mips_frame_cache *cache;
if ((*this_cache) != NULL)
- return (*this_cache);
+ return (struct mips_frame_cache *) (*this_cache);
cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
(*this_cache) = cache;
if (start_addr == 0)
return cache;
- micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
+ micromips_scan_prologue (gdbarch, start_addr, pc, this_frame,
+ (struct mips_frame_cache *) *this_cache);
}
/* gdbarch_sp_regnum contains the value and not the address. */
gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
cache->base);
- return (*this_cache);
+ return (struct mips_frame_cache *) (*this_cache);
}
static void
frame_offset = 0;
for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
{
- unsigned long inst, high_word, low_word;
+ unsigned long inst, high_word;
+ long offset;
int reg;
this_non_prologue_insn = 0;
/* Save some code by pre-extracting some useful fields. */
high_word = (inst >> 16) & 0xffff;
- low_word = inst & 0xffff;
+ offset = ((inst & 0xffff) ^ 0x8000) - 0x8000;
reg = high_word & 0x1f;
if (high_word == 0x27bd /* addiu $sp,$sp,-i */
|| high_word == 0x23bd /* addi $sp,$sp,-i */
|| high_word == 0x67bd) /* daddiu $sp,$sp,-i */
{
- if (low_word & 0x8000) /* Negative stack adjustment? */
- frame_offset += 0x10000 - low_word;
+ if (offset < 0) /* Negative stack adjustment? */
+ frame_offset -= offset;
else
/* Exit loop if a positive stack adjustment is found, which
usually means that the stack cleanup code in the function
else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
&& !regsize_is_64_bits)
{
- set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
+ set_reg_offset (gdbarch, this_cache, reg, sp + offset);
}
else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
&& regsize_is_64_bits)
{
/* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
- set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
+ set_reg_offset (gdbarch, this_cache, reg, sp + offset);
}
else if (high_word == 0x27be) /* addiu $30,$sp,size */
{
/* Old gcc frame, r30 is virtual frame pointer. */
- if ((long) low_word != frame_offset)
- frame_addr = sp + low_word;
+ if (offset != frame_offset)
+ frame_addr = sp + offset;
else if (this_frame && frame_reg == MIPS_SP_REGNUM)
{
unsigned alloca_adjust;
(this_frame, gdbarch_num_regs (gdbarch) + 30);
frame_offset = 0;
- alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
+ alloca_adjust = (unsigned) (frame_addr - (sp + offset));
if (alloca_adjust > 0)
{
/* FP > SP + frame_size. This may be because of
else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
&& !regsize_is_64_bits)
{
- set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word);
+ set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
}
else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
|| (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
struct mips_frame_cache *cache;
if ((*this_cache) != NULL)
- return (*this_cache);
+ return (struct mips_frame_cache *) (*this_cache);
cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
(*this_cache) = cache;
if (start_addr == 0)
return cache;
- mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
+ mips32_scan_prologue (gdbarch, start_addr, pc, this_frame,
+ (struct mips_frame_cache *) *this_cache);
}
/* gdbarch_sp_regnum contains the value and not the address. */
gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
cache->base);
- return (*this_cache);
+ return (struct mips_frame_cache *) (*this_cache);
}
static void
int num_regs = gdbarch_num_regs (gdbarch);
if ((*this_cache) != NULL)
- return (*this_cache);
+ return (struct trad_frame_cache *) (*this_cache);
this_trad_cache = trad_frame_cache_zalloc (this_frame);
(*this_cache) = this_trad_cache;
msym = lookup_minimal_symbol_by_pc (pc);
if (msym.minsym != NULL
&& MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL
- && strncmp (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.", 5) == 0)
+ && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
return 1;
return 0;
its destination address. */
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
- /* 48-bit instructions. */
- case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
- loc += 2 * MIPS_INSN16_SIZE;
- break;
-
/* 32-bit instructions. */
case 2 * MIPS_INSN16_SIZE:
switch (micromips_op (insn))
{
struct gdbarch *gdbarch = get_frame_arch (frame);
int raw_size = register_size (gdbarch, regno);
- gdb_byte *raw_buffer = alloca (raw_size);
+ gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size);
if (!deprecated_frame_register_read (frame, regno, raw_buffer))
error (_("can't read register %d (%s)"),
double doub, flt1; /* Doubles extracted from raw hex data. */
int inv1, inv2;
- raw_buffer = alloca (2 * register_size (gdbarch,
- mips_regnum (gdbarch)->fp0));
+ raw_buffer
+ = ((gdb_byte *)
+ alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)));
fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
fprintf_filtered (file, "%*s",
&opts, 0, file);
}
+/* Print IEEE exception condition bits in FLAGS. */
+
+static void
+print_fpu_flags (struct ui_file *file, int flags)
+{
+ if (flags & (1 << 0))
+ fputs_filtered (" inexact", file);
+ if (flags & (1 << 1))
+ fputs_filtered (" uflow", file);
+ if (flags & (1 << 2))
+ fputs_filtered (" oflow", file);
+ if (flags & (1 << 3))
+ fputs_filtered (" div0", file);
+ if (flags & (1 << 4))
+ fputs_filtered (" inval", file);
+ if (flags & (1 << 5))
+ fputs_filtered (" unimp", file);
+ fputc_filtered ('\n', file);
+}
+
+/* Print interesting information about the floating point processor
+ (if present) or emulator. */
+
+static void
+mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
+ struct frame_info *frame, const char *args)
+{
+ int fcsr = mips_regnum (gdbarch)->fp_control_status;
+ enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch);
+ ULONGEST fcs = 0;
+ int i;
+
+ if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs))
+ type = MIPS_FPU_NONE;
+
+ fprintf_filtered (file, "fpu type: %s\n",
+ type == MIPS_FPU_DOUBLE ? "double-precision"
+ : type == MIPS_FPU_SINGLE ? "single-precision"
+ : "none / unused");
+
+ if (type == MIPS_FPU_NONE)
+ return;
+
+ fprintf_filtered (file, "reg size: %d bits\n",
+ register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8);
+
+ fputs_filtered ("cond :", file);
+ if (fcs & (1 << 23))
+ fputs_filtered (" 0", file);
+ for (i = 1; i <= 7; i++)
+ if (fcs & (1 << (24 + i)))
+ fprintf_filtered (file, " %d", i);
+ fputc_filtered ('\n', file);
+
+ fputs_filtered ("cause :", file);
+ print_fpu_flags (file, (fcs >> 12) & 0x3f);
+ fputs ("mask :", stdout);
+ print_fpu_flags (file, (fcs >> 7) & 0x1f);
+ fputs ("flags :", stdout);
+ print_fpu_flags (file, (fcs >> 2) & 0x1f);
+
+ fputs_filtered ("rounding: ", file);
+ switch (fcs & 3)
+ {
+ case 0: fputs_filtered ("nearest\n", file); break;
+ case 1: fputs_filtered ("zero\n", file); break;
+ case 2: fputs_filtered ("+inf\n", file); break;
+ case 3: fputs_filtered ("-inf\n", file); break;
+ }
+
+ fputs_filtered ("flush :", file);
+ if (fcs & (1 << 21))
+ fputs_filtered (" nearest", file);
+ if (fcs & (1 << 22))
+ fputs_filtered (" override", file);
+ if (fcs & (1 << 24))
+ fputs_filtered (" zero", file);
+ if ((fcs & (0xb << 21)) == 0)
+ fputs_filtered (" no", file);
+ fputc_filtered ('\n', file);
+
+ fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no");
+ fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no");
+ fputc_filtered ('\n', file);
+
+ default_print_float_info (gdbarch, file, frame, args);
+}
+
/* Replacement for generic do_registers_info.
Print regs in pretty columns. */
return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
}
-/* Check whether the PC is in a function epilogue (32-bit version).
- This is a helper function for mips_in_function_epilogue_p. */
+/* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
+ This is a helper function for mips_stack_frame_destroyed_p. */
+
static int
-mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR func_addr = 0, func_end = 0;
return 0;
}
-/* Check whether the PC is in a function epilogue (microMIPS version).
- This is a helper function for mips_in_function_epilogue_p. */
+/* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
+ This is a helper function for mips_stack_frame_destroyed_p. */
static int
-micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR func_addr = 0;
CORE_ADDR func_end = 0;
loc += MIPS_INSN16_SIZE;
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
- /* 48-bit instructions. */
- case 3 * MIPS_INSN16_SIZE:
- /* No epilogue instructions in this category. */
- return 0;
-
/* 32-bit instructions. */
case 2 * MIPS_INSN16_SIZE:
insn <<= 16;
return 1;
}
-/* Check whether the PC is in a function epilogue (16-bit version).
- This is a helper function for mips_in_function_epilogue_p. */
+/* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
+ This is a helper function for mips_stack_frame_destroyed_p. */
+
static int
-mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR func_addr = 0, func_end = 0;
return 0;
}
-/* The epilogue is defined here as the area at the end of a function,
+/* Implement the stack_frame_destroyed_p gdbarch method.
+
+ The epilogue is defined here as the area at the end of a function,
after an instruction which destroys the function's stack frame. */
+
static int
-mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
if (mips_pc_is_mips16 (gdbarch, pc))
- return mips16_in_function_epilogue_p (gdbarch, pc);
+ return mips16_stack_frame_destroyed_p (gdbarch, pc);
else if (mips_pc_is_micromips (gdbarch, pc))
- return micromips_in_function_epilogue_p (gdbarch, pc);
+ return micromips_stack_frame_destroyed_p (gdbarch, pc);
else
- return mips32_in_function_epilogue_p (gdbarch, pc);
+ return mips32_stack_frame_destroyed_p (gdbarch, pc);
}
/* Root of all "set mips "/"show mips " commands. This will eventually be
static int
gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
{
- struct gdbarch *gdbarch = info->application_data;
+ struct gdbarch *gdbarch = (struct gdbarch *) info->application_data;
/* FIXME: cagney/2003-06-26: Is this even necessary? The
disassembler needs to be able to locally determine the ISA, and
static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 };
static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 };
ULONGEST insn;
- int status;
+ int err;
int size;
- insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
- size = status ? 2
- : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
+ insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err);
+ size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn);
*pcptr = unmake_compact_addr (pc);
*lenptr = size;
return (size == 2) ? micromips16_big_breakpoint
static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 };
static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 };
ULONGEST insn;
- int status;
+ int err;
int size;
- insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
- size = status ? 2
- : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
+ insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err);
+ size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn);
*pcptr = unmake_compact_addr (pc);
*lenptr = size;
return (size == 2) ? micromips16_little_breakpoint
{
ULONGEST insn;
int status;
+ int size;
insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
if (status)
return 0;
+ size = mips_insn_size (ISA_MICROMIPS, insn);
insn <<= 16;
- if (mips_insn_size (ISA_MICROMIPS, insn) == 2 * MIPS_INSN16_SIZE)
+ if (size == 2 * MIPS_INSN16_SIZE)
{
insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
if (status)
/* If the PC is in __call_stub_* or __fn_stub*, this is one of the
compiler-generated call or call/return stubs. */
- if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0
- || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0)
+ if (startswith (name, mips_str_fn_stub)
+ || startswith (name, mips_str_call_stub))
{
if (pc == start_addr)
/* This is the 'call' part of a call stub. Call this helper
if (msym.minsym == NULL
|| BMSYMBOL_VALUE_ADDRESS (msym) != pc
|| MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL
- || strncmp (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.", 5) != 0)
+ || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
return 0;
/* A two-instruction header. */
else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78)
regnum = num + mips_regnum (gdbarch)->dspacc - 72;
else
- /* This will hopefully (eventually) provoke a warning. Should
- we be calling complaint() here? */
- return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
+ return -1;
return gdbarch_num_regs (gdbarch) + regnum;
}
else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72)
regnum = num + mips_regnum (gdbarch)->dspacc - 66;
else
- /* This will hopefully (eventually) provoke a warning. Should we
- be calling complaint() here? */
- return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
+ return -1;
return gdbarch_num_regs (gdbarch) + regnum;
}
if (*abip != MIPS_ABI_UNKNOWN)
return;
- if (strncmp (name, ".mdebug.", 8) != 0)
+ if (!startswith (name, ".mdebug."))
return;
if (strcmp (name, ".mdebug.abi32") == 0)
int *lbp = (int *) obj;
const char *name = bfd_get_section_name (abfd, sect);
- if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
+ if (startswith (name, ".gcc_compiled_long32"))
*lbp = 32;
- else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
+ else if (startswith (name, ".gcc_compiled_long64"))
*lbp = 64;
- else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
+ else if (startswith (name, ".gcc_compiled_long"))
warning (_("unrecognized .gcc_compiled_longXX"));
}
static struct value *
value_of_mips_user_reg (struct frame_info *frame, const void *baton)
{
- const int *reg_p = baton;
+ const int *reg_p = (const int *) baton;
return value_of_register (*reg_p, frame);
}
}
/* Need a new architecture. Fill in a target specific vector. */
- tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
+ tdep = XNEW (struct gdbarch_tdep);
gdbarch = gdbarch_alloc (&info, tdep);
tdep->elf_flags = elf_flags;
tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code);
set_gdbarch_frame_align (gdbarch, mips_frame_align);
+ set_gdbarch_print_float_info (gdbarch, mips_print_float_info);
+
set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
- set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
+ set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p);
set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
mips_register_g_packet_guesses (gdbarch);
/* Hook in OS ABI-specific overrides, if they have been registered. */
- info.tdep_info = (void *) tdesc_data;
+ info.tdep_info = tdesc_data;
gdbarch_init_osabi (info, gdbarch);
/* The hook may have adjusted num_regs, fetch the final value and
projects / deliverable / binutils-gdb.git / blobdiff