return ((addr) & ~(CORE_ADDR) 1);
}
-/* Return the contents of register REGNUM as a signed integer. */
-
-static LONGEST
-read_signed_register (int regnum)
-{
- LONGEST val;
- regcache_cooked_read_signed (current_regcache, regnum, &val);
- return val;
-}
-
-static LONGEST
-read_signed_register_pid (int regnum, ptid_t ptid)
-{
- ptid_t save_ptid;
- LONGEST retval;
-
- if (ptid_equal (ptid, inferior_ptid))
- return read_signed_register (regnum);
-
- save_ptid = inferior_ptid;
-
- inferior_ptid = ptid;
-
- retval = read_signed_register (regnum);
-
- inferior_ptid = save_ptid;
-
- return retval;
-}
-
/* Return the MIPS ABI associated with GDBARCH. */
enum mips_abi
mips_abi (struct gdbarch *gdbarch)
all registers should be sign extended for simplicity? */
static CORE_ADDR
-mips_read_pc (ptid_t ptid)
+mips_read_pc (struct regcache *regcache)
{
- return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid);
+ ULONGEST pc;
+ int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
+ regcache_cooked_read_signed (regcache, regnum, &pc);
+ return pc;
}
static CORE_ADDR
}
static void
-mips_write_pc (CORE_ADDR pc, ptid_t ptid)
+mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
{
- write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid);
+ int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
+ regcache_cooked_write_unsigned (regcache, regnum, pc);
}
/* Fetch and return instruction from the specified location. If the PC
/* Determine where to set a single step breakpoint while considering
branch prediction. */
static CORE_ADDR
-mips32_next_pc (CORE_ADDR pc)
+mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
{
unsigned long inst;
int op;
int tf = itype_rt (inst) & 0x01;
int cnum = itype_rt (inst) >> 2;
int fcrcs =
- read_signed_register (mips_regnum (current_gdbarch)->
- fp_control_status);
+ get_frame_register_signed (frame, mips_regnum (current_gdbarch)->
+ fp_control_status);
int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
if (((cond >> cnum) & 0x01) == tf)
case 8: /* JR */
case 9: /* JALR */
/* Set PC to that address */
- pc = read_signed_register (rtype_rs (inst));
+ pc = get_frame_register_signed (frame, rtype_rs (inst));
break;
default:
pc += 4;
case 16: /* BLTZAL */
case 18: /* BLTZALL */
less_branch:
- if (read_signed_register (itype_rs (inst)) < 0)
+ if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
pc += mips32_relative_offset (inst) + 4;
else
pc += 8; /* after the delay slot */
case 3: /* BGEZL */
case 17: /* BGEZAL */
case 19: /* BGEZALL */
- if (read_signed_register (itype_rs (inst)) >= 0)
+ if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
pc += mips32_relative_offset (inst) + 4;
else
pc += 8; /* after the delay slot */
break; /* The new PC will be alternate mode */
case 4: /* BEQ, BEQL */
equal_branch:
- if (read_signed_register (itype_rs (inst)) ==
- read_signed_register (itype_rt (inst)))
+ if (get_frame_register_signed (frame, itype_rs (inst)) ==
+ get_frame_register_signed (frame, itype_rt (inst)))
pc += mips32_relative_offset (inst) + 4;
else
pc += 8;
break;
case 5: /* BNE, BNEL */
neq_branch:
- if (read_signed_register (itype_rs (inst)) !=
- read_signed_register (itype_rt (inst)))
+ if (get_frame_register_signed (frame, itype_rs (inst)) !=
+ get_frame_register_signed (frame, itype_rt (inst)))
pc += mips32_relative_offset (inst) + 4;
else
pc += 8;
break;
case 6: /* BLEZ, BLEZL */
- if (read_signed_register (itype_rs (inst)) <= 0)
+ if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
pc += mips32_relative_offset (inst) + 4;
else
pc += 8;
case 7:
default:
greater_branch: /* BGTZ, BGTZL */
- if (read_signed_register (itype_rs (inst)) > 0)
+ if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
pc += mips32_relative_offset (inst) + 4;
else
pc += 8;
}
static CORE_ADDR
-extended_mips16_next_pc (CORE_ADDR pc,
+extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
unsigned int extension, unsigned int insn)
{
int op = (insn >> 11);
struct upk_mips16 upk;
int reg;
unpack_mips16 (pc, extension, insn, ritype, &upk);
- reg = read_signed_register (upk.regx);
+ reg = get_frame_register_signed (frame, upk.regx);
if (reg == 0)
pc += (upk.offset << 1) + 2;
else
struct upk_mips16 upk;
int reg;
unpack_mips16 (pc, extension, insn, ritype, &upk);
- reg = read_signed_register (upk.regx);
+ reg = get_frame_register_signed (frame, upk.regx);
if (reg != 0)
pc += (upk.offset << 1) + 2;
else
int reg;
unpack_mips16 (pc, extension, insn, i8type, &upk);
/* upk.regx contains the opcode */
- reg = read_signed_register (24); /* Test register is 24 */
+ reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
|| ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
/* pc = add_offset_16(pc,upk.offset) ; */
reg = 31;
break; /* BOGUS Guess */
}
- pc = read_signed_register (reg);
+ pc = get_frame_register_signed (frame, reg);
}
else
pc += 2;
that. */
{
pc += 2;
- pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
+ pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc));
break;
}
default:
}
static CORE_ADDR
-mips16_next_pc (CORE_ADDR pc)
+mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
{
unsigned int insn = fetch_mips_16 (pc);
- return extended_mips16_next_pc (pc, 0, insn);
+ return extended_mips16_next_pc (frame, pc, 0, insn);
}
/* The mips_next_pc function supports single_step when the remote
branch will go. This isnt hard because all the data is available.
The MIPS32 and MIPS16 variants are quite different */
static CORE_ADDR
-mips_next_pc (CORE_ADDR pc)
+mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
{
if (pc & 0x01)
- return mips16_next_pc (pc);
+ return mips16_next_pc (frame, pc);
else
- return mips32_next_pc (pc);
+ return mips32_next_pc (frame, pc);
}
struct mips_frame_cache
mips16_scan_prologue (start_addr, pc, next_frame, *this_cache);
}
- /* SP_REGNUM, contains the value and not the address. */
+ /* gdbarch_sp_regnum contains the value and not the address. */
trad_frame_set_value (cache->saved_regs, gdbarch_num_regs (current_gdbarch)
+ MIPS_SP_REGNUM, cache->base);
mips32_scan_prologue (start_addr, pc, next_frame, *this_cache);
}
- /* SP_REGNUM, contains the value and not the address. */
+ /* gdbarch_sp_regnum contains the value and not the address. */
trad_frame_set_value (cache->saved_regs,
gdbarch_num_regs (current_gdbarch) + MIPS_SP_REGNUM,
cache->base);
(*this_cache) = this_trad_cache;
/* The return address is in the link register. */
- trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM);
+ trad_frame_set_reg_realreg (this_trad_cache,
+ gdbarch_pc_regnum (current_gdbarch),
+ MIPS_RA_REGNUM);
/* Frame ID, since it's a frameless / stackless function, no stack
space is allocated and SP on entry is the current SP. */
the target of the coming instruction and breakpoint it. */
int
-mips_software_single_step (struct regcache *regcache)
+mips_software_single_step (struct frame_info *frame)
{
CORE_ADDR pc, next_pc;
- pc = read_register (mips_regnum (current_gdbarch)->pc);
- next_pc = mips_next_pc (pc);
+ pc = get_frame_pc (frame);
+ next_pc = mips_next_pc (frame, pc);
insert_single_step_breakpoint (next_pc);
return 1;
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
ULONGEST prid;
- regcache_cooked_read_unsigned (current_regcache,
+ regcache_cooked_read_unsigned (get_current_regcache (),
MIPS_PRID_REGNUM, &prid);
if ((prid & ~0xf) == 0x700)
tdep->mips_processor_reg_names = mips_r3041_reg_names;
gory details. */
static CORE_ADDR
-mips_skip_trampoline_code (CORE_ADDR pc)
+mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
{
char *name;
CORE_ADDR start_addr;
target PC is in $31 ($ra). */
if (strcmp (name, "__mips16_ret_sf") == 0
|| strcmp (name, "__mips16_ret_df") == 0)
- return read_signed_register (MIPS_RA_REGNUM);
+ return get_frame_register_signed (frame, MIPS_RA_REGNUM);
if (strncmp (name, "__mips16_call_stub_", 19) == 0)
{
/* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
and the target PC is in $2. */
if (name[19] >= '0' && name[19] <= '9')
- return read_signed_register (2);
+ return get_frame_register_signed (frame, 2);
/* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
before the jal instruction, this is effectively a call stub
So scan down to the lui/addi and extract the target
address from those two instructions. */
- CORE_ADDR target_pc = read_signed_register (2);
+ CORE_ADDR target_pc = get_frame_register_signed (frame, 2);
ULONGEST inst;
int i;
else
/* This is the 'return' part of a call stub. The return
address is in $r18. */
- return read_signed_register (18);
+ return get_frame_register_signed (frame, 18);
}
}
return 0; /* not a stub */
else
reg_names = mips_generic_reg_names;
}
- /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
+ /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
replaced by read_pc? */
set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
projects / deliverable / binutils-gdb.git / blobdiff