#include "objfiles.h"
#include "gdbtypes.h"
#include "target.h"
+#include "arch-utils.h"
#include "opcode/mips.h"
+#include "elf/mips.h"
+#include "elf-bfd.h"
+
struct frame_extra_info
{
int num_args;
};
+/* We allow the user to override MIPS_SAVED_REGSIZE, so define
+ the subcommand enum settings allowed. */
+static char saved_gpreg_size_auto[] = "auto";
+static char saved_gpreg_size_32[] = "32";
+static char saved_gpreg_size_64[] = "64";
+
+static char *saved_gpreg_size_enums[] = {
+ saved_gpreg_size_auto,
+ saved_gpreg_size_32,
+ saved_gpreg_size_64,
+ 0
+};
+
+/* The current (string) value of saved_gpreg_size. */
+static char *mips_saved_regsize_string = saved_gpreg_size_auto;
+
/* Some MIPS boards don't support floating point while others only
support single-precision floating-point operations. See also
FP_REGISTER_DOUBLE. */
static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
#define MIPS_FPU_TYPE mips_fpu_type
-#ifndef MIPS_SAVED_REGSIZE
-#define MIPS_SAVED_REGSIZE MIPS_REGSIZE
+#ifndef MIPS_DEFAULT_SAVED_REGSIZE
+#define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
#endif
+#define MIPS_SAVED_REGSIZE (mips_saved_regsize())
+
/* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
#ifndef FP_REGISTER_DOUBLE
#define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
#endif
+/* MIPS specific per-architecture information */
+struct gdbarch_tdep
+ {
+ /* from the elf header */
+ int elf_flags;
+ /* mips options */
+ int mips_eabi;
+ enum mips_fpu_type mips_fpu_type;
+ int mips_last_arg_regnum;
+ int mips_last_fp_arg_regnum;
+ int mips_default_saved_regsize;
+ int mips_fp_register_double;
+ };
+
+#if GDB_MULTI_ARCH
+#undef MIPS_EABI
+#define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_eabi)
+#endif
+
+#if GDB_MULTI_ARCH
+#undef MIPS_LAST_FP_ARG_REGNUM
+#define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
+#endif
+
+#if GDB_MULTI_ARCH
+#undef MIPS_LAST_ARG_REGNUM
+#define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
+#endif
+
+#if GDB_MULTI_ARCH
+#undef MIPS_FPU_TYPE
+#define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
+#endif
+
+#if GDB_MULTI_ARCH
+#undef MIPS_DEFAULT_SAVED_REGSIZE
+#define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
+#endif
+
+/* Indicate that the ABI makes use of double-precision registers
+ provided by the FPU (rather than combining pairs of registers to
+ form double-precision values). Do not use "TARGET_IS_MIPS64" to
+ determine if the ABI is using double-precision registers. See also
+ MIPS_FPU_TYPE. */
+#if GDB_MULTI_ARCH
+#undef FP_REGISTER_DOUBLE
+#define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
+#endif
+
+
#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
#if 0
char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
char **mips_processor_reg_names = mips_generic_reg_names;
+/* The list of available "set mips " and "show mips " commands */
+static struct cmd_list_element *setmipscmdlist = NULL;
+static struct cmd_list_element *showmipscmdlist = NULL;
+
char *
mips_register_name (i)
int i;
paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
}
+/* Return the currently configured (or set) saved register size */
+
+static unsigned int
+mips_saved_regsize ()
+{
+ if (mips_saved_regsize_string == saved_gpreg_size_auto)
+ return MIPS_DEFAULT_SAVED_REGSIZE;
+ else if (mips_saved_regsize_string == saved_gpreg_size_64)
+ return 8;
+ else /* if (mips_saved_regsize_string == saved_gpreg_size_32) */
+ return 4;
+}
+
/* Convert between RAW and VIRTUAL registers. The RAW register size
defines the remote-gdb packet. */
gdb_stdout, 0, 1, 0, Val_pretty_default);
/* Else print as integer in hex. */
else
- print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum),
- 'x', 0, gdb_stdout);
+ {
+ int offset;
+
+ if (TARGET_BYTE_ORDER == BIG_ENDIAN)
+ offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
+ else
+ offset = 0;
+
+ print_scalar_formatted (raw_buffer + offset,
+ REGISTER_VIRTUAL_TYPE (regnum),
+ 'x', 0, gdb_stdout);
+ }
}
/* Replacement for generic do_registers_info.
regnum + 1, REGISTER_NAME (regnum + 1));
/* copy the two floats into one double, and unpack both */
- memcpy (dbl_buffer, raw_buffer, sizeof (dbl_buffer));
+ memcpy (dbl_buffer, raw_buffer, 2 * REGISTER_RAW_SIZE (FP0_REGNUM));
flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1);
flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2);
doub = unpack_double (builtin_type_double, dbl_buffer, &inv3);
{ /* eight byte registers: print each one as float AND as double. */
int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN);
- memcpy (dbl_buffer, raw_buffer[HI], sizeof (dbl_buffer));
+ memcpy (dbl_buffer, raw_buffer[HI], 2 * REGISTER_RAW_SIZE (FP0_REGNUM));
flt1 = unpack_double (builtin_type_float,
&raw_buffer[HI][offset], &inv1);
doub = unpack_double (builtin_type_double, dbl_buffer, &inv3);
return (pc >= sigtramp_address && pc < sigtramp_end);
}
+/* Root of all "set mips "/"show mips " commands. This will eventually be
+ used for all MIPS-specific commands. */
+
+static void show_mips_command PARAMS ((char *, int));
+static void
+show_mips_command (args, from_tty)
+ char *args;
+ int from_tty;
+{
+ help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
+}
+
+static void set_mips_command PARAMS ((char *, int));
+static void
+set_mips_command (args, from_tty)
+ char *args;
+ int from_tty;
+{
+ printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
+ help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
+}
+
/* Commands to show/set the MIPS FPU type. */
static void show_mipsfpu_command PARAMS ((char *, int));
{
mips_fpu_type = MIPS_FPU_SINGLE;
mips_fpu_type_auto = 0;
+ if (GDB_MULTI_ARCH)
+ {
+ gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
+ }
}
static void set_mipsfpu_double_command PARAMS ((char *, int));
{
mips_fpu_type = MIPS_FPU_DOUBLE;
mips_fpu_type_auto = 0;
+ if (GDB_MULTI_ARCH)
+ {
+ gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
+ }
}
static void set_mipsfpu_none_command PARAMS ((char *, int));
{
mips_fpu_type = MIPS_FPU_NONE;
mips_fpu_type_auto = 0;
+ if (GDB_MULTI_ARCH)
+ {
+ gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
+ }
}
static void set_mipsfpu_auto_command PARAMS ((char *, int));
}
+/* If the current gcc for for this target does not produce correct debugging
+ information for float parameters, both prototyped and unprototyped, then
+ define this macro. This forces gdb to always assume that floats are
+ passed as doubles and then converted in the callee.
+
+ For the mips chip, it appears that the debug info marks the parameters as
+ floats regardless of whether the function is prototyped, but the actual
+ values are passed as doubles for the non-prototyped case and floats for
+ the prototyped case. Thus we choose to make the non-prototyped case work
+ for C and break the prototyped case, since the non-prototyped case is
+ probably much more common. (FIXME). */
+
+static int
+mips_coerce_float_to_double (struct type *formal, struct type *actual)
+{
+ return current_language->la_language == language_c;
+}
+
+
+static gdbarch_init_ftype mips_gdbarch_init;
+static struct gdbarch *
+mips_gdbarch_init (info, arches)
+ struct gdbarch_info info;
+ struct gdbarch_list *arches;
+{
+ static LONGEST mips_call_dummy_words[] =
+ {0};
+ struct gdbarch *gdbarch;
+ struct gdbarch_tdep *tdep;
+ int elf_flags;
+ char *ef_mips_abi;
+ int ef_mips_bitptrs;
+ int ef_mips_arch;
+
+ /* Extract the elf_flags if available */
+ if (info.abfd != NULL
+ && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
+ elf_flags = elf_elfheader (info.abfd)->e_flags;
+ else
+ elf_flags = 0;
+
+ /* try to find a pre-existing architecture */
+ for (arches = gdbarch_list_lookup_by_info (arches, &info);
+ arches != NULL;
+ arches = gdbarch_list_lookup_by_info (arches->next, &info))
+ {
+ /* MIPS needs to be pedantic about which ABI the object is
+ using. */
+ if (gdbarch_tdep (current_gdbarch)->elf_flags != elf_flags)
+ continue;
+ return arches->gdbarch;
+ }
+
+ /* Need a new architecture. Fill in a target specific vector. */
+ tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
+ gdbarch = gdbarch_alloc (&info, tdep);
+ tdep->elf_flags = elf_flags;
+
+ /* Initially set everything according to the ABI. */
+ set_gdbarch_short_bit (gdbarch, 16);
+ set_gdbarch_int_bit (gdbarch, 32);
+ set_gdbarch_float_bit (gdbarch, 32);
+ set_gdbarch_double_bit (gdbarch, 64);
+ set_gdbarch_long_double_bit (gdbarch, 64);
+ switch ((elf_flags & EF_MIPS_ABI))
+ {
+ case E_MIPS_ABI_O32:
+ ef_mips_abi = "o32";
+ tdep->mips_eabi = 0;
+ tdep->mips_default_saved_regsize = 4;
+ tdep->mips_fp_register_double = 0;
+ set_gdbarch_long_bit (gdbarch, 32);
+ set_gdbarch_ptr_bit (gdbarch, 32);
+ set_gdbarch_long_long_bit (gdbarch, 64);
+ break;
+ case E_MIPS_ABI_O64:
+ ef_mips_abi = "o64";
+ tdep->mips_eabi = 0;
+ tdep->mips_default_saved_regsize = 8;
+ tdep->mips_fp_register_double = 1;
+ set_gdbarch_long_bit (gdbarch, 32);
+ set_gdbarch_ptr_bit (gdbarch, 32);
+ set_gdbarch_long_long_bit (gdbarch, 64);
+ break;
+ case E_MIPS_ABI_EABI32:
+ ef_mips_abi = "eabi32";
+ tdep->mips_eabi = 1;
+ tdep->mips_default_saved_regsize = 4;
+ tdep->mips_fp_register_double = 0;
+ set_gdbarch_long_bit (gdbarch, 32);
+ set_gdbarch_ptr_bit (gdbarch, 32);
+ set_gdbarch_long_long_bit (gdbarch, 64);
+ break;
+ case E_MIPS_ABI_EABI64:
+ ef_mips_abi = "eabi64";
+ tdep->mips_eabi = 1;
+ tdep->mips_default_saved_regsize = 8;
+ tdep->mips_fp_register_double = 1;
+ set_gdbarch_long_bit (gdbarch, 64);
+ set_gdbarch_ptr_bit (gdbarch, 64);
+ set_gdbarch_long_long_bit (gdbarch, 64);
+ break;
+ default:
+ ef_mips_abi = "default";
+ tdep->mips_eabi = 0;
+ tdep->mips_default_saved_regsize = MIPS_REGSIZE;
+ tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8);
+ set_gdbarch_long_bit (gdbarch, 32);
+ set_gdbarch_ptr_bit (gdbarch, 32);
+ set_gdbarch_long_long_bit (gdbarch, 64);
+ break;
+ }
+
+ /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
+ that could indicate -gp32 BUT gas/config/tc-mips.c contains the
+ comment:
+
+ ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
+ flag in object files because to do so would make it impossible to
+ link with libraries compiled without "-gp32". This is
+ unnecessarily restrictive.
+
+ We could solve this problem by adding "-gp32" multilibs to gcc,
+ but to set this flag before gcc is built with such multilibs will
+ break too many systems.''
+
+ But even more unhelpfully, the default linker output target for
+ mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
+ for 64-bit programs - you need to change the ABI to change this,
+ and not all gcc targets support that currently. Therefore using
+ this flag to detect 32-bit mode would do the wrong thing given
+ the current gcc - it would make GDB treat these 64-bit programs
+ as 32-bit programs by default. */
+
+ /* determine the ISA */
+ switch (elf_flags & EF_MIPS_ARCH)
+ {
+ case E_MIPS_ARCH_1:
+ ef_mips_arch = 1;
+ break;
+ case E_MIPS_ARCH_2:
+ ef_mips_arch = 2;
+ break;
+ case E_MIPS_ARCH_3:
+ ef_mips_arch = 3;
+ break;
+ case E_MIPS_ARCH_4:
+ ef_mips_arch = 0;
+ break;
+ default:
+ break;
+ }
+
+#if 0
+ /* determine the size of a pointer */
+ if ((elf_flags & EF_MIPS_32BITPTRS))
+ {
+ ef_mips_bitptrs = 32;
+ }
+ else if ((elf_flags & EF_MIPS_64BITPTRS))
+ {
+ ef_mips_bitptrs = 64;
+ }
+ else
+ {
+ ef_mips_bitptrs = 0;
+ }
+#endif
+
+ /* Select either of the two alternative ABI's */
+ if (tdep->mips_eabi)
+ {
+ /* EABI uses R4 through R11 for args */
+ tdep->mips_last_arg_regnum = 11;
+ /* EABI uses F12 through F19 for args */
+ tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
+ }
+ else
+ {
+ /* old ABI uses R4 through R7 for args */
+ tdep->mips_last_arg_regnum = 7;
+ /* old ABI uses F12 through F15 for args */
+ tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
+ }
+
+ /* enable/disable the MIPS FPU */
+ if (!mips_fpu_type_auto)
+ tdep->mips_fpu_type = mips_fpu_type;
+ else if (info.bfd_arch_info != NULL
+ && info.bfd_arch_info->arch == bfd_arch_mips)
+ switch (info.bfd_arch_info->mach)
+ {
+ case bfd_mach_mips4100:
+ case bfd_mach_mips4111:
+ tdep->mips_fpu_type = MIPS_FPU_NONE;
+ break;
+ default:
+ tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
+ break;
+ }
+ else
+ tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
+
+ /* MIPS version of register names. NOTE: At present the MIPS
+ register name management is part way between the old -
+ #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
+ Further work on it is required. */
+ set_gdbarch_register_name (gdbarch, mips_register_name);
+ set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
+ set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
+ set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
+ set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
+ set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
+ set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
+
+ /* Initialize a frame */
+ set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
+
+ /* MIPS version of CALL_DUMMY */
+
+ set_gdbarch_call_dummy_p (gdbarch, 1);
+ set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
+ set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
+ set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
+ set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
+ set_gdbarch_call_dummy_start_offset (gdbarch, 0);
+ set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
+ set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
+ set_gdbarch_call_dummy_length (gdbarch, 0);
+ set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
+ set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
+ set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
+ set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
+ set_gdbarch_push_arguments (gdbarch, mips_push_arguments);
+ set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not);
+ set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double);
+
+ set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
+ set_gdbarch_get_saved_register (gdbarch, default_get_saved_register);
+
+ if (gdbarch_debug)
+ {
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: (info)elf_flags = 0x%x\n",
+ elf_flags);
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: (info)ef_mips_abi = %s\n",
+ ef_mips_abi);
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: (info)ef_mips_arch = %d\n",
+ ef_mips_arch);
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: (info)ef_mips_bitptrs = %d\n",
+ ef_mips_bitptrs);
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: MIPS_EABI = %d\n",
+ tdep->mips_eabi);
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: MIPS_LAST_ARG_REGNUM = %d\n",
+ tdep->mips_last_arg_regnum);
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: MIPS_LAST_FP_ARG_REGNUM = %d (%d)\n",
+ tdep->mips_last_fp_arg_regnum,
+ tdep->mips_last_fp_arg_regnum - FP0_REGNUM);
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n",
+ tdep->mips_fpu_type,
+ (tdep->mips_fpu_type == MIPS_FPU_NONE ? "none"
+ : tdep->mips_fpu_type == MIPS_FPU_SINGLE ? "single"
+ : tdep->mips_fpu_type == MIPS_FPU_DOUBLE ? "double"
+ : "???"));
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: tdep->mips_default_saved_regsize = %d\n",
+ tdep->mips_default_saved_regsize);
+ fprintf_unfiltered (gdb_stderr,
+ "mips_gdbarch_init: tdep->mips_fp_register_double = %d (%s)\n",
+ tdep->mips_fp_register_double,
+ (tdep->mips_fp_register_double ? "true" : "false"));
+ }
+
+ return gdbarch;
+}
+
void
_initialize_mips_tdep ()
static struct cmd_list_element *mipsfpulist = NULL;
struct cmd_list_element *c;
+ if (GDB_MULTI_ARCH)
+ register_gdbarch_init (bfd_arch_mips, mips_gdbarch_init);
if (!tm_print_insn) /* Someone may have already set it */
tm_print_insn = gdb_print_insn_mips;
+ /* Add root prefix command for all "set mips"/"show mips" commands */
+ add_prefix_cmd ("mips", no_class, set_mips_command,
+ "Various MIPS specific commands.",
+ &setmipscmdlist, "set mips ", 0, &setlist);
+
+ add_prefix_cmd ("mips", no_class, show_mips_command,
+ "Various MIPS specific commands.",
+ &showmipscmdlist, "show mips ", 0, &showlist);
+
+ /* Allow the user to override the saved register size. */
+ add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
+ class_obscure,
+ saved_gpreg_size_enums,
+ (char *) &mips_saved_regsize_string, "\
+Set size of general purpose registers saved on the stack.\n\
+This option can be set to one of:\n\
+ 32 - Force GDB to treat saved GP registers as 32-bit\n\
+ 64 - Force GDB to treat saved GP registers as 64-bit\n\
+ auto - Allow GDB to use the target's default setting or autodetect the\n\
+ saved GP register size from information contained in the executable.\n\
+ (default: auto)",
+ &setmipscmdlist),
+ &showmipscmdlist);
+
/* Let the user turn off floating point and set the fence post for
heuristic_proc_start. */
"Show current use of MIPS floating-point coprocessor target.",
&showlist);
+#if !GDB_MULTI_ARCH
c = add_set_cmd ("processor", class_support, var_string_noescape,
(char *) &tmp_mips_processor_type,
"Set the type of MIPS processor in use.\n\
tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE);
mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0);
+#endif
/* We really would like to have both "0" and "unlimited" work, but
command.c doesn't deal with that. So make it a var_zinteger
projects / deliverable / binutils-gdb.git / blobdiff