int register_size;
};
-static int
-n32n64_floatformat_always_valid (const struct floatformat *fmt,
- const void *from)
-{
- return 1;
-}
-
-/* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
- They are implemented as a pair of 64bit doubles where the high
- part holds the result of the operation rounded to double, and
- the low double holds the difference between the exact result and
- the rounded result. So "high" + "low" contains the result with
- added precision. Unfortunately, the floatformat structure used
- by GDB is not powerful enough to describe this format. As a temporary
- measure, we define a 128bit floatformat that only uses the high part.
- We lose a bit of precision but that's probably the best we can do
- for now with the current infrastructure. */
-
-static const struct floatformat floatformat_n32n64_long_double_big =
-{
- floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52,
- floatformat_intbit_no,
- "floatformat_n32n64_long_double_big",
- n32n64_floatformat_always_valid
-};
-
-static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] =
-{
- &floatformat_n32n64_long_double_big,
- &floatformat_n32n64_long_double_big
-};
-
const struct mips_regnum *
mips_regnum (struct gdbarch *gdbarch)
{
things accordingly. */
static void
-mips_xfer_register (struct regcache *regcache, int reg_num, int length,
+mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_num, int length,
enum bfd_endian endian, gdb_byte *in,
const gdb_byte *out, int buf_offset)
{
int reg_offset = 0;
- gdb_assert (reg_num >= gdbarch_num_regs (current_gdbarch));
+
+ gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
/* Need to transfer the left or right part of the register, based on
the targets byte order. */
switch (endian)
{
case BFD_ENDIAN_BIG:
- reg_offset = register_size (current_gdbarch, reg_num) - length;
+ reg_offset = register_size (gdbarch, reg_num) - length;
break;
case BFD_ENDIAN_LITTLE:
reg_offset = 0;
static int
mips2_fp_compat (struct frame_info *frame)
{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
/* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
meaningful. */
- if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) ==
- 4)
+ if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
return 0;
#if 0
/* Return the name of the register corresponding to REGNO. */
static const char *
-mips_register_name (int regno)
+mips_register_name (struct gdbarch *gdbarch, int regno)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* GPR names for all ABIs other than n32/n64. */
static char *mips_gpr_names[] = {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
- enum mips_abi abi = mips_abi (current_gdbarch);
+ enum mips_abi abi = mips_abi (gdbarch);
/* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
but then don't make the raw register names visible. */
- int rawnum = regno % gdbarch_num_regs (current_gdbarch);
- if (regno < gdbarch_num_regs (current_gdbarch))
+ int rawnum = regno % gdbarch_num_regs (gdbarch);
+ if (regno < gdbarch_num_regs (gdbarch))
return "";
/* The MIPS integer registers are always mapped from 0 to 31. The
else
return mips_gpr_names[rawnum];
}
- else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch)))
- return tdesc_register_name (rawnum);
- else if (32 <= rawnum && rawnum < gdbarch_num_regs (current_gdbarch))
+ else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
+ return tdesc_register_name (gdbarch, rawnum);
+ else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
{
gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
return tdep->mips_processor_reg_names[rawnum - 32];
int vector_p;
int float_p;
int raw_p;
- int rawnum = regnum % gdbarch_num_regs (current_gdbarch);
- int pseudo = regnum / gdbarch_num_regs (current_gdbarch);
+ int rawnum = regnum % gdbarch_num_regs (gdbarch);
+ int pseudo = regnum / gdbarch_num_regs (gdbarch);
if (reggroup == all_reggroup)
return pseudo;
vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
/* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
(gdbarch), as not all architectures are multi-arch. */
- raw_p = rawnum < gdbarch_num_regs (current_gdbarch);
- if (gdbarch_register_name (current_gdbarch, regnum) == NULL
- || gdbarch_register_name (current_gdbarch, regnum)[0] == '\0')
+ raw_p = rawnum < gdbarch_num_regs (gdbarch);
+ if (gdbarch_register_name (gdbarch, regnum) == NULL
+ || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
return 0;
if (reggroup == float_reggroup)
return float_p && pseudo;
mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
int cookednum, gdb_byte *buf)
{
- int rawnum = cookednum % gdbarch_num_regs (current_gdbarch);
- gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch)
- && cookednum < 2 * gdbarch_num_regs (current_gdbarch));
+ int rawnum = cookednum % gdbarch_num_regs (gdbarch);
+ gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
+ && cookednum < 2 * gdbarch_num_regs (gdbarch));
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
regcache_raw_read (regcache, rawnum, buf);
else if (register_size (gdbarch, rawnum) >
register_size (gdbarch, cookednum))
{
if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
- || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
+ || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
else
regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
struct regcache *regcache, int cookednum,
const gdb_byte *buf)
{
- int rawnum = cookednum % gdbarch_num_regs (current_gdbarch);
- gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch)
- && cookednum < 2 * gdbarch_num_regs (current_gdbarch));
+ int rawnum = cookednum % gdbarch_num_regs (gdbarch);
+ gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
+ && cookednum < 2 * gdbarch_num_regs (gdbarch));
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
regcache_raw_write (regcache, rawnum, buf);
else if (register_size (gdbarch, rawnum) >
register_size (gdbarch, cookednum))
{
if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
- || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
+ || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
else
regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
/* Convert to/from a register and the corresponding memory value. */
static int
-mips_convert_register_p (int regnum, struct type *type)
-{
- return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
- && register_size (current_gdbarch, regnum) == 4
- && (regnum % gdbarch_num_regs (current_gdbarch))
- >= mips_regnum (current_gdbarch)->fp0
- && (regnum % gdbarch_num_regs (current_gdbarch))
- < mips_regnum (current_gdbarch)->fp0 + 32
+mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
+{
+ return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
+ && register_size (gdbarch, regnum) == 4
+ && (regnum % gdbarch_num_regs (gdbarch))
+ >= mips_regnum (gdbarch)->fp0
+ && (regnum % gdbarch_num_regs (gdbarch))
+ < mips_regnum (gdbarch)->fp0 + 32
&& TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
}
static struct type *
mips_register_type (struct gdbarch *gdbarch, int regnum)
{
- gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (current_gdbarch));
- if ((regnum % gdbarch_num_regs (current_gdbarch))
- >= mips_regnum (current_gdbarch)->fp0
- && (regnum % gdbarch_num_regs (current_gdbarch))
- < mips_regnum (current_gdbarch)->fp0 + 32)
+ gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
+ if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0
+ && (regnum % gdbarch_num_regs (gdbarch))
+ < mips_regnum (gdbarch)->fp0 + 32)
{
/* The floating-point registers raw, or cooked, always match
mips_isa_regsize(), and also map 1:1, byte for byte. */
else
return builtin_type_ieee_double;
}
- else if (regnum < gdbarch_num_regs (current_gdbarch))
+ else if (regnum < gdbarch_num_regs (gdbarch))
{
/* The raw or ISA registers. These are all sized according to
the ISA regsize. */
{
/* The cooked or ABI registers. These are sized according to
the ABI (with a few complications). */
- if (regnum >= (gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp_control_status)
- && regnum <= gdbarch_num_regs (current_gdbarch)
- + MIPS_LAST_EMBED_REGNUM)
+ if (regnum >= (gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp_control_status)
+ && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM)
/* The pseudo/cooked view of the embedded registers is always
32-bit. The raw view is handled below. */
return builtin_type_int32;
static CORE_ADDR
mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
- return frame_unwind_register_signed (next_frame,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (gdbarch)->pc);
+ return frame_unwind_register_signed
+ (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc);
}
static CORE_ADDR
mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
- return frame_unwind_register_signed (next_frame,
- gdbarch_num_regs (current_gdbarch)
- + MIPS_SP_REGNUM);
+ return frame_unwind_register_signed
+ (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
}
/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
{
return frame_id_build
(frame_unwind_register_signed (next_frame,
- gdbarch_num_regs (current_gdbarch)
+ gdbarch_num_regs (gdbarch)
+ MIPS_SP_REGNUM),
frame_pc_unwind (next_frame));
}
goto neq_branch;
case 2: /* BLEZL */
goto less_branch;
- case 3: /* BGTZ */
+ case 3: /* BGTZL */
goto greater_branch;
default:
pc += 4;
int tf = itype_rt (inst) & 0x01;
int cnum = itype_rt (inst) >> 2;
int fcrcs =
- get_frame_register_signed (frame, mips_regnum (current_gdbarch)->
+ get_frame_register_signed (frame,
+ mips_regnum (get_frame_arch (frame))->
fp_control_status);
int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
int extend_bytes = 0;
int prev_extend_bytes;
CORE_ADDR end_prologue_addr = 0;
+ struct gdbarch *gdbarch = get_frame_arch (next_frame);
/* Can be called when there's no process, and hence when there's no
NEXT_FRAME. */
if (next_frame != NULL)
sp = frame_unwind_register_signed (next_frame,
- gdbarch_num_regs (current_gdbarch)
+ gdbarch_num_regs (gdbarch)
+ MIPS_SP_REGNUM);
else
sp = 0;
for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
{
set_reg_offset (this_cache, reg, sp + offset);
- offset += mips_abi_regsize (current_gdbarch);
+ offset += mips_abi_regsize (gdbarch);
}
/* Check if the ra register was pushed on the stack. */
if (entry_inst & 0x20)
{
set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
- offset -= mips_abi_regsize (current_gdbarch);
+ offset -= mips_abi_regsize (gdbarch);
}
/* Check if the s0 and s1 registers were pushed on the stack. */
for (reg = 16; reg < sreg_count + 16; reg++)
{
set_reg_offset (this_cache, reg, sp + offset);
- offset -= mips_abi_regsize (current_gdbarch);
+ offset -= mips_abi_regsize (gdbarch);
}
}
{
this_cache->base =
(frame_unwind_register_signed (next_frame,
- gdbarch_num_regs (current_gdbarch)
- + frame_reg)
+ gdbarch_num_regs (gdbarch) + frame_reg)
+ frame_offset - frame_adjust);
/* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
be able to get rid of the assignment below, evetually. But it's
still needed for now. */
- this_cache->saved_regs[gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->pc]
- = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch)
- + MIPS_RA_REGNUM];
+ this_cache->saved_regs[gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->pc]
+ = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
}
/* If we didn't reach the end of the prologue when scanning the function
}
/* gdbarch_sp_regnum contains the value and not the address. */
- trad_frame_set_value (cache->saved_regs, gdbarch_num_regs (current_gdbarch)
- + MIPS_SP_REGNUM, cache->base);
+ trad_frame_set_value (cache->saved_regs,
+ gdbarch_num_regs (get_frame_arch (next_frame))
+ + MIPS_SP_REGNUM,
+ cache->base);
return (*this_cache);
}
CORE_ADDR end_prologue_addr = 0;
int seen_sp_adjust = 0;
int load_immediate_bytes = 0;
+ struct gdbarch *gdbarch = get_frame_arch (next_frame);
/* Can be called when there's no process, and hence when there's no
NEXT_FRAME. */
if (next_frame != NULL)
sp = frame_unwind_register_signed (next_frame,
- gdbarch_num_regs (current_gdbarch)
+ gdbarch_num_regs (gdbarch)
+ MIPS_SP_REGNUM);
else
sp = 0;
frame_reg = 30;
frame_addr = frame_unwind_register_signed
- (next_frame,
- gdbarch_num_regs (current_gdbarch) + 30);
+ (next_frame, gdbarch_num_regs (gdbarch) + 30);
alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
if (alloca_adjust > 0)
frame_reg = 30;
frame_addr = frame_unwind_register_signed
- (next_frame,
- gdbarch_num_regs (current_gdbarch) + 30);
+ (next_frame, gdbarch_num_regs (gdbarch) + 30);
alloca_adjust = (unsigned) (frame_addr - sp);
if (alloca_adjust > 0)
{
this_cache->base =
(frame_unwind_register_signed (next_frame,
- gdbarch_num_regs (current_gdbarch)
- + frame_reg)
+ gdbarch_num_regs (gdbarch) + frame_reg)
+ frame_offset);
/* FIXME: brobecker/2004-09-15: We should be able to get rid of
this assignment below, eventually. But it's still needed
for now. */
- this_cache->saved_regs[gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->pc]
- = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch)
+ this_cache->saved_regs[gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->pc]
+ = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
+ MIPS_RA_REGNUM];
}
/* gdbarch_sp_regnum contains the value and not the address. */
trad_frame_set_value (cache->saved_regs,
- gdbarch_num_regs (current_gdbarch) + MIPS_SP_REGNUM,
+ gdbarch_num_regs (get_frame_arch (next_frame))
+ + MIPS_SP_REGNUM,
cache->base);
return (*this_cache);
CORE_ADDR start_addr;
CORE_ADDR stack_addr;
struct trad_frame_cache *this_trad_cache;
+ struct gdbarch *gdbarch = get_frame_arch (next_frame);
if ((*this_cache) != NULL)
return (*this_cache);
/* The return address is in the link register. */
trad_frame_set_reg_realreg (this_trad_cache,
- gdbarch_pc_regnum (current_gdbarch),
- (gdbarch_num_regs (current_gdbarch)
- + MIPS_RA_REGNUM));
+ gdbarch_pc_regnum (gdbarch),
+ (gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM));
/* Frame ID, since it's a frameless / stackless function, no stack
space is allocated and SP on entry is the current SP. */
return addr;
}
+/* Instructions used during single-stepping of atomic sequences. */
+#define LL_OPCODE 0x30
+#define LLD_OPCODE 0x34
+#define SC_OPCODE 0x38
+#define SCD_OPCODE 0x3c
+
+/* Checks for an atomic sequence of instructions beginning with a LL/LLD
+ instruction and ending with a SC/SCD instruction. If such a sequence
+ is found, attempt to step through it. A breakpoint is placed at the end of
+ the sequence. */
+
+static int
+deal_with_atomic_sequence (CORE_ADDR pc)
+{
+ CORE_ADDR breaks[2] = {-1, -1};
+ CORE_ADDR loc = pc;
+ CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
+ unsigned long insn;
+ int insn_count;
+ int index;
+ int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
+ const int atomic_sequence_length = 16; /* Instruction sequence length. */
+
+ if (pc & 0x01)
+ return 0;
+
+ insn = mips_fetch_instruction (loc);
+ /* Assume all atomic sequences start with a ll/lld instruction. */
+ if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
+ return 0;
+
+ /* Assume that no atomic sequence is longer than "atomic_sequence_length"
+ instructions. */
+ for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
+ {
+ int is_branch = 0;
+ loc += MIPS_INSN32_SIZE;
+ insn = mips_fetch_instruction (loc);
+
+ /* Assume that there is at most one branch in the atomic
+ sequence. If a branch is found, put a breakpoint in its
+ destination address. */
+ switch (itype_op (insn))
+ {
+ case 0: /* SPECIAL */
+ if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
+ return 0; /* fallback to the standard single-step code. */
+ break;
+ case 1: /* REGIMM */
+ is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */
+ break;
+ case 2: /* J */
+ case 3: /* JAL */
+ return 0; /* fallback to the standard single-step code. */
+ case 4: /* BEQ */
+ case 5: /* BNE */
+ case 6: /* BLEZ */
+ case 7: /* BGTZ */
+ case 20: /* BEQL */
+ case 21: /* BNEL */
+ case 22: /* BLEZL */
+ case 23: /* BGTTL */
+ is_branch = 1;
+ break;
+ case 17: /* COP1 */
+ case 18: /* COP2 */
+ case 19: /* COP3 */
+ is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
+ break;
+ }
+ if (is_branch)
+ {
+ branch_bp = loc + mips32_relative_offset (insn) + 4;
+ if (last_breakpoint >= 1)
+ return 0; /* More than one branch found, fallback to the
+ standard single-step code. */
+ breaks[1] = branch_bp;
+ last_breakpoint++;
+ }
+
+ if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
+ break;
+ }
+
+ /* Assume that the atomic sequence ends with a sc/scd instruction. */
+ if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
+ return 0;
+
+ loc += MIPS_INSN32_SIZE;
+
+ /* Insert a breakpoint right after the end of the atomic sequence. */
+ breaks[0] = loc;
+
+ /* Check for duplicated breakpoints. Check also for a breakpoint
+ placed (branch instruction's destination) in the atomic sequence */
+ if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
+ last_breakpoint = 0;
+
+ /* Effectively inserts the breakpoints. */
+ for (index = 0; index <= last_breakpoint; index++)
+ insert_single_step_breakpoint (breaks[index]);
+
+ return 1;
+}
+
/* mips_software_single_step() is called just before we want to resume
the inferior, if we want to single-step it but there is no hardware
or kernel single-step support (MIPS on GNU/Linux for example). We find
CORE_ADDR pc, next_pc;
pc = get_frame_pc (frame);
+ if (deal_with_atomic_sequence (pc))
+ return 1;
+
next_pc = mips_next_pc (frame, pc);
insert_single_step_breakpoint (next_pc);
/* Initialize the integer and float register pointers. */
argreg = MIPS_A0_REGNUM;
- float_argreg = mips_fpa0_regnum (current_gdbarch);
+ float_argreg = mips_fpa0_regnum (gdbarch);
/* The struct_return pointer occupies the first parameter-passing reg. */
if (struct_return)
making the ABI determination. */
if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
{
- int low_offset = gdbarch_byte_order (current_gdbarch)
+ int low_offset = gdbarch_byte_order (gdbarch)
== BFD_ENDIAN_BIG ? 4 : 0;
unsigned long regval;
int longword_offset = 0;
CORE_ADDR addr;
stack_used_p = 1;
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
if (regsize == 8
&& (typecode == TYPE_CODE_INT
/* Initialize the integer and float register pointers. */
argreg = MIPS_A0_REGNUM;
- float_argreg = mips_fpa0_regnum (current_gdbarch);
+ float_argreg = mips_fpa0_regnum (gdbarch);
/* The struct_return pointer occupies the first parameter-passing reg. */
if (struct_return)
int longword_offset = 0;
CORE_ADDR addr;
stack_used_p = 1;
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
if ((typecode == TYPE_CODE_INT
|| typecode == TYPE_CODE_PTR
It does not seem to be necessary to do the
same for integral types. */
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
&& partial_len < MIPS64_REGSIZE
&& (typecode == TYPE_CODE_STRUCT
|| typecode == TYPE_CODE_UNION))
struct type *type, struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
eight bytes with the lower memory address are in $f0. */
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0,
- 8, gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0,
+ 8, gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0 + 2,
- 8, gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0 + 2,
+ 8, gdbarch_byte_order (gdbarch),
readbuf ? readbuf + 8 : readbuf,
writebuf ? writebuf + 8 : writebuf, 0);
return RETURN_VALUE_REGISTER_CONVENTION;
else if (TYPE_CODE (type) == TYPE_CODE_FLT
&& tdep->mips_fpu_type != MIPS_FPU_NONE)
{
- /* A floating-point value belongs in the least significant part
- of FP0. */
+ /* A single or double floating-point value that fits in FP0. */
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0,
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0,
TYPE_LENGTH (type),
- gdbarch_byte_order (current_gdbarch),
+ gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
return RETURN_VALUE_REGISTER_CONVENTION;
}
register.. */
int regnum;
int field;
- for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
+ for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
field < TYPE_NFIELDS (type); field++, regnum += 2)
{
int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
offset);
- mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch)
- + regnum,
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch) + regnum,
TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
- gdbarch_byte_order (current_gdbarch),
+ gdbarch_byte_order (gdbarch),
readbuf, writebuf, offset);
}
return RETURN_VALUE_REGISTER_CONVENTION;
int regnum;
for (offset = 0, regnum = MIPS_V0_REGNUM;
offset < TYPE_LENGTH (type);
- offset += register_size (current_gdbarch, regnum), regnum++)
+ offset += register_size (gdbarch, regnum), regnum++)
{
- int xfer = register_size (current_gdbarch, regnum);
+ int xfer = register_size (gdbarch, regnum);
if (offset + xfer > TYPE_LENGTH (type))
xfer = TYPE_LENGTH (type) - offset;
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
offset, xfer, regnum);
- mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch)
- + regnum, xfer,
- BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch) + regnum,
+ xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
+ offset);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
int regnum;
for (offset = 0, regnum = MIPS_V0_REGNUM;
offset < TYPE_LENGTH (type);
- offset += register_size (current_gdbarch, regnum), regnum++)
+ offset += register_size (gdbarch, regnum), regnum++)
{
- int xfer = register_size (current_gdbarch, regnum);
+ int xfer = register_size (gdbarch, regnum);
if (offset + xfer > TYPE_LENGTH (type))
xfer = TYPE_LENGTH (type) - offset;
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
offset, xfer, regnum);
- mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch)
- + regnum, xfer,
- gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch) + regnum,
+ xfer, gdbarch_byte_order (gdbarch),
readbuf, writebuf, offset);
}
return RETURN_VALUE_REGISTER_CONVENTION;
/* Initialize the integer and float register pointers. */
argreg = MIPS_A0_REGNUM;
- float_argreg = mips_fpa0_regnum (current_gdbarch);
+ float_argreg = mips_fpa0_regnum (gdbarch);
/* The struct_return pointer occupies the first parameter-passing reg. */
if (struct_return)
{
if (register_size (gdbarch, float_argreg) < 8 && len == 8)
{
- int low_offset = gdbarch_byte_order (current_gdbarch)
+ int low_offset = gdbarch_byte_order (gdbarch)
== BFD_ENDIAN_BIG ? 4 : 0;
unsigned long regval;
identified as such and GDB gets tweaked
accordingly. */
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
&& partial_len < MIPS32_REGSIZE
&& (typecode == TYPE_CODE_STRUCT
|| typecode == TYPE_CODE_UNION))
struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION
least significant part of FP0. */
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0,
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0,
TYPE_LENGTH (type),
- gdbarch_byte_order (current_gdbarch),
+ gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
return RETURN_VALUE_REGISTER_CONVENTION;
}
FP0. */
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
- switch (gdbarch_byte_order (current_gdbarch))
+ switch (gdbarch_byte_order (gdbarch))
{
case BFD_ENDIAN_LITTLE:
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0 +
- 0, 4, gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0 +
+ 0, 4, gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0 + 1,
- 4, gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0 + 1,
+ 4, gdbarch_byte_order (gdbarch),
readbuf, writebuf, 4);
break;
case BFD_ENDIAN_BIG:
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0 + 1,
- 4, gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0 + 1,
+ 4, gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0 + 0,
- 4, gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0 + 0,
+ 4, gdbarch_byte_order (gdbarch),
readbuf, writebuf, 4);
break;
default:
gdb_byte reg[MAX_REGISTER_SIZE];
int regnum;
int field;
- for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
+ for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
field < TYPE_NFIELDS (type); field++, regnum += 2)
{
int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
offset);
- mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch)
- + regnum,
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch) + regnum,
TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
- gdbarch_byte_order (current_gdbarch),
+ gdbarch_byte_order (gdbarch),
readbuf, writebuf, offset);
}
return RETURN_VALUE_REGISTER_CONVENTION;
int regnum;
for (offset = 0, regnum = MIPS_V0_REGNUM;
offset < TYPE_LENGTH (type);
- offset += register_size (current_gdbarch, regnum), regnum++)
+ offset += register_size (gdbarch, regnum), regnum++)
{
- int xfer = register_size (current_gdbarch, regnum);
+ int xfer = register_size (gdbarch, regnum);
if (offset + xfer > TYPE_LENGTH (type))
xfer = TYPE_LENGTH (type) - offset;
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
offset, xfer, regnum);
- mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch)
- + regnum, xfer,
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch) + regnum, xfer,
BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
}
return RETURN_VALUE_REGISTER_CONVENTION;
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
offset, xfer, regnum);
- mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch)
- + regnum, xfer,
- gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch) + regnum, xfer,
+ gdbarch_byte_order (gdbarch),
readbuf, writebuf, offset);
}
return RETURN_VALUE_REGISTER_CONVENTION;
/* Initialize the integer and float register pointers. */
argreg = MIPS_A0_REGNUM;
- float_argreg = mips_fpa0_regnum (current_gdbarch);
+ float_argreg = mips_fpa0_regnum (gdbarch);
/* The struct_return pointer occupies the first parameter-passing reg. */
if (struct_return)
int longword_offset = 0;
CORE_ADDR addr;
stack_used_p = 1;
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
if ((typecode == TYPE_CODE_INT
|| typecode == TYPE_CODE_PTR
It does not seem to be necessary to do the
same for integral types. */
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
&& partial_len < MIPS64_REGSIZE
&& (typecode == TYPE_CODE_STRUCT
|| typecode == TYPE_CODE_UNION))
struct type *type, struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION
part of FP0. */
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
- mips_xfer_register (regcache,
- gdbarch_num_regs (current_gdbarch)
- + mips_regnum (current_gdbarch)->fp0,
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0,
TYPE_LENGTH (type),
- gdbarch_byte_order (current_gdbarch),
+ gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
return RETURN_VALUE_REGISTER_CONVENTION;
}
if (mips_debug)
fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
offset, xfer, regnum);
- mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch)
- + regnum, xfer,
- gdbarch_byte_order (current_gdbarch),
+ mips_xfer_register (gdbarch, regcache,
+ gdbarch_num_regs (gdbarch) + regnum,
+ xfer, gdbarch_byte_order (gdbarch),
readbuf, writebuf, offset);
}
return RETURN_VALUE_REGISTER_CONVENTION;
mips_read_fp_register_single (struct frame_info *frame, int regno,
gdb_byte *rare_buffer)
{
- int raw_size = register_size (current_gdbarch, regno);
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ int raw_size = register_size (gdbarch, regno);
gdb_byte *raw_buffer = alloca (raw_size);
if (!frame_register_read (frame, regno, raw_buffer))
error (_("can't read register %d (%s)"),
- regno, gdbarch_register_name (current_gdbarch, regno));
+ regno, gdbarch_register_name (gdbarch, regno));
if (raw_size == 8)
{
/* We have a 64-bit value for this register. Find the low-order
32 bits. */
int offset;
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
offset = 4;
else
offset = 0;
mips_read_fp_register_double (struct frame_info *frame, int regno,
gdb_byte *rare_buffer)
{
- int raw_size = register_size (current_gdbarch, regno);
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ int raw_size = register_size (gdbarch, regno);
if (raw_size == 8 && !mips2_fp_compat (frame))
{
all 64 bits. */
if (!frame_register_read (frame, regno, rare_buffer))
error (_("can't read register %d (%s)"),
- regno, gdbarch_register_name (current_gdbarch, regno));
+ regno, gdbarch_register_name (gdbarch, regno));
}
else
{
- if ((regno - mips_regnum (current_gdbarch)->fp0) & 1)
+ int rawnum = regno % gdbarch_num_regs (gdbarch);
+
+ if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
internal_error (__FILE__, __LINE__,
_("mips_read_fp_register_double: bad access to "
"odd-numbered FP register"));
/* mips_read_fp_register_single will find the correct 32 bits from
each register. */
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
mips_read_fp_register_single (frame, regno, rare_buffer + 4);
mips_read_fp_register_single (frame, regno + 1, rare_buffer);
mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
int regnum)
{ /* do values for FP (float) regs */
+ struct gdbarch *gdbarch = get_frame_arch (frame);
gdb_byte *raw_buffer;
double doub, flt1; /* doubles extracted from raw hex data */
int inv1, inv2;
- raw_buffer = alloca (2 * register_size (current_gdbarch,
- mips_regnum (current_gdbarch)->fp0));
+ raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0));
- fprintf_filtered (file, "%s:",
- gdbarch_register_name (current_gdbarch, regnum));
+ fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
fprintf_filtered (file, "%*s",
- 4 - (int) strlen (gdbarch_register_name
- (current_gdbarch, regnum)),
+ 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
"");
- if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat (frame))
+ if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
{
/* 4-byte registers: Print hex and floating. Also print even
numbered registers as doubles. */
else
fprintf_filtered (file, "%-17.9g", flt1);
- if (regnum % 2 == 0)
+ if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
{
mips_read_fp_register_double (frame, regnum, raw_buffer);
doub = unpack_double (mips_double_register_type (), raw_buffer,
if (!frame_register_read (frame, regnum, raw_buffer))
{
fprintf_filtered (file, "%s: [Invalid]",
- gdbarch_register_name (current_gdbarch, regnum));
+ gdbarch_register_name (gdbarch, regnum));
return;
}
- fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file);
+ fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
/* The problem with printing numeric register names (r26, etc.) is that
the user can't use them on input. Probably the best solution is to
else
fprintf_filtered (file, ": ");
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
offset =
- register_size (current_gdbarch,
- regnum) - register_size (current_gdbarch, regnum);
+ register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
else
offset = 0;
/* For GP registers, we print a separate row of names above the vals */
for (col = 0, regnum = start_regnum;
- col < ncols && regnum < gdbarch_num_regs (current_gdbarch)
- + gdbarch_num_pseudo_regs (current_gdbarch);
+ col < ncols && regnum < gdbarch_num_regs (gdbarch)
+ + gdbarch_num_pseudo_regs (gdbarch);
regnum++)
{
- if (*gdbarch_register_name (current_gdbarch, regnum) == '\0')
+ if (*gdbarch_register_name (gdbarch, regnum) == '\0')
continue; /* unused register */
if (TYPE_CODE (register_type (gdbarch, regnum)) ==
TYPE_CODE_FLT)
break; /* end the row: reached FP register */
/* Large registers are handled separately. */
- if (register_size (current_gdbarch, regnum)
- > mips_abi_regsize (current_gdbarch))
+ if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
{
if (col > 0)
break; /* End the row before this register. */
if (col == 0)
fprintf_filtered (file, " ");
fprintf_filtered (file,
- mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
- gdbarch_register_name (current_gdbarch, regnum));
+ mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
+ gdbarch_register_name (gdbarch, regnum));
col++;
}
return regnum;
/* print the R0 to R31 names */
- if ((start_regnum % gdbarch_num_regs (current_gdbarch)) < MIPS_NUMREGS)
+ if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
fprintf_filtered (file, "\n R%-4d",
- start_regnum % gdbarch_num_regs (current_gdbarch));
+ start_regnum % gdbarch_num_regs (gdbarch));
else
fprintf_filtered (file, "\n ");
/* now print the values in hex, 4 or 8 to the row */
for (col = 0, regnum = start_regnum;
- col < ncols && regnum < gdbarch_num_regs (current_gdbarch)
- + gdbarch_num_pseudo_regs (current_gdbarch);
+ col < ncols && regnum < gdbarch_num_regs (gdbarch)
+ + gdbarch_num_pseudo_regs (gdbarch);
regnum++)
{
- if (*gdbarch_register_name (current_gdbarch, regnum) == '\0')
+ if (*gdbarch_register_name (gdbarch, regnum) == '\0')
continue; /* unused register */
if (TYPE_CODE (register_type (gdbarch, regnum)) ==
TYPE_CODE_FLT)
break; /* end row: reached FP register */
- if (register_size (current_gdbarch, regnum)
- > mips_abi_regsize (current_gdbarch))
+ if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
break; /* End row: large register. */
/* OK: get the data in raw format. */
if (!frame_register_read (frame, regnum, raw_buffer))
error (_("can't read register %d (%s)"),
- regnum, gdbarch_register_name (current_gdbarch, regnum));
+ regnum, gdbarch_register_name (gdbarch, regnum));
/* pad small registers */
for (byte = 0;
- byte < (mips_abi_regsize (current_gdbarch)
- - register_size (current_gdbarch, regnum)); byte++)
+ byte < (mips_abi_regsize (gdbarch)
+ - register_size (gdbarch, regnum)); byte++)
printf_filtered (" ");
/* Now print the register value in hex, endian order. */
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
for (byte =
- register_size (current_gdbarch,
- regnum) - register_size (current_gdbarch, regnum);
- byte < register_size (current_gdbarch, regnum); byte++)
+ register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
+ byte < register_size (gdbarch, regnum); byte++)
fprintf_filtered (file, "%02x", raw_buffer[byte]);
else
- for (byte = register_size (current_gdbarch, regnum) - 1;
+ for (byte = register_size (gdbarch, regnum) - 1;
byte >= 0; byte--)
fprintf_filtered (file, "%02x", raw_buffer[byte]);
fprintf_filtered (file, " ");
{
if (regnum != -1) /* do one specified register */
{
- gdb_assert (regnum >= gdbarch_num_regs (current_gdbarch));
- if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0')
+ gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
+ if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
error (_("Not a valid register for the current processor type"));
mips_print_register (file, frame, regnum);
else
/* do all (or most) registers */
{
- regnum = gdbarch_num_regs (current_gdbarch);
- while (regnum < gdbarch_num_regs (current_gdbarch)
- + gdbarch_num_pseudo_regs (current_gdbarch))
+ regnum = gdbarch_num_regs (gdbarch);
+ while (regnum < gdbarch_num_regs (gdbarch)
+ + gdbarch_num_pseudo_regs (gdbarch))
{
if (TYPE_CODE (register_type (gdbarch, regnum)) ==
TYPE_CODE_FLT)
should be inserted. */
static const gdb_byte *
-mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
+mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
{
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
if (mips_pc_is_mips16 (*pcptr))
{
return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type));
}
+/* Dummy virtual frame pointer method. This is no more or less accurate
+ than most other architectures; we just need to be explicit about it,
+ because the pseudo-register gdbarch_sp_regnum will otherwise lead to
+ an assertion failure. */
+
+static void
+mips_virtual_frame_pointer (struct gdbarch *gdbarch,
+ CORE_ADDR pc, int *reg, LONGEST *offset)
+{
+ *reg = MIPS_SP_REGNUM;
+ *offset = 0;
+}
+
static void
mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
{
set_gdbarch_num_regs (gdbarch, num_regs);
set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
set_gdbarch_register_name (gdbarch, mips_register_name);
+ set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
tdep->mips_processor_reg_names = reg_names;
tdep->regnum = regnum;
}
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_long_double_bit (gdbarch, 128);
- set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long);
+ set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
break;
case MIPS_ABI_N64:
set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
set_gdbarch_ptr_bit (gdbarch, 64);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_long_double_bit (gdbarch, 128);
- set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long);
+ set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
break;
default:
internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
if (tdesc_data)
{
set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
- tdesc_use_registers (gdbarch, tdesc_data);
+ tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
/* Override the normal target description methods to handle our
dual real and pseudo registers. */
}
static void
-mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
+mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep != NULL)
{
int ef_mips_arch;
projects / deliverable / binutils-gdb.git / blobdiff