testsuite: Fix for gcc-4.8: gdb.base/jit.exp gdb.base/jit-so.exp

[deliverable/binutils-gdb.git] / gdb / mips-tdep.c

diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index ca17864f68b5fa6be3dbcf57016d35af215939f8..c2bf0c01dc03fae2d3d16b5e191a0a83605b12c8 100644 (file)
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -1518,10 +1518,8 @@ mips_insn_size (enum mips_isa isa, ULONGEST insn)
   switch (isa)
     {
     case ISA_MICROMIPS:
-      if (micromips_op (insn) == 0x1f)
-        return 3 * MIPS_INSN16_SIZE;
-      else if (((micromips_op (insn) & 0x4) == 0x4)
-              || ((micromips_op (insn) & 0x7) == 0x0))
+      if ((micromips_op (insn) & 0x4) == 0x4
+         || (micromips_op (insn) & 0x7) == 0x0)
         return 2 * MIPS_INSN16_SIZE;
       else
         return MIPS_INSN16_SIZE;
@@ -1881,12 +1879,6 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
   pc += MIPS_INSN16_SIZE;
   switch (mips_insn_size (ISA_MICROMIPS, insn))
     {
-    /* 48-bit instructions.  */
-    case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
-      /* No branch or jump instructions in this category.  */
-      pc += 2 * MIPS_INSN16_SIZE;
-      break;
-
     /* 32-bit instructions.  */
     case 2 * MIPS_INSN16_SIZE:
       insn <<= 16;
@@ -2993,13 +2985,6 @@ micromips_scan_prologue (struct gdbarch *gdbarch,
       loc += MIPS_INSN16_SIZE;
       switch (mips_insn_size (ISA_MICROMIPS, insn))
        {
-       /* 48-bit instructions.  */
-       case 3 * MIPS_INSN16_SIZE:
-         /* No prologue instructions in this category.  */
-         this_non_prologue_insn = 1;
-         loc += 2 * MIPS_INSN16_SIZE;
-         break;
-
        /* 32-bit instructions.  */
        case 2 * MIPS_INSN16_SIZE:
          insn <<= 16;
@@ -4041,11 +4026,6 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
          its destination address.  */
       switch (mips_insn_size (ISA_MICROMIPS, insn))
        {
-       /* 48-bit instructions.  */
-       case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
-         loc += 2 * MIPS_INSN16_SIZE;
-         break;
-
        /* 32-bit instructions.  */
        case 2 * MIPS_INSN16_SIZE:
          switch (micromips_op (insn))
@@ -6769,11 +6749,6 @@ micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
       loc += MIPS_INSN16_SIZE;
       switch (mips_insn_size (ISA_MICROMIPS, insn))
        {
-       /* 48-bit instructions.  */
-       case 3 * MIPS_INSN16_SIZE:
-         /* No epilogue instructions in this category.  */
-         return 0;
-
        /* 32-bit instructions.  */
        case 2 * MIPS_INSN16_SIZE:
          insn <<= 16;
@@ -7006,25 +6981,6 @@ set_mipsfpu_auto_command (char *args, int from_tty)
   mips_fpu_type_auto = 1;
 }
 
-/* Attempt to identify the particular processor model by reading the
-   processor id.  NOTE: cagney/2003-11-15: Firstly it isn't clear that
-   the relevant processor still exists (it dates back to '94) and
-   secondly this is not the way to do this.  The processor type should
-   be set by forcing an architecture change.  */
-
-void
-deprecated_mips_set_processor_regs_hack (void)
-{
-  struct regcache *regcache = get_current_regcache ();
-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-  ULONGEST prid;
-
-  regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid);
-  if ((prid & ~0xf) == 0x700)
-    tdep->mips_processor_reg_names = mips_r3041_reg_names;
-}
-
 /* Just like reinit_frame_cache, but with the right arguments to be
    callable as an sfunc.  */
 
@@ -7122,9 +7078,7 @@ mips_breakpoint_from_pc (struct gdbarch *gdbarch,
          int size;
 
          insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err);
-         size = (err != 0
-                 ? 2 : (mips_insn_size (ISA_MICROMIPS, insn) == 2
-                        ? 2 : 4));
+         size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn);
          *pcptr = unmake_compact_addr (pc);
          *lenptr = size;
          return (size == 2) ? micromips16_big_breakpoint
@@ -7174,9 +7128,7 @@ mips_breakpoint_from_pc (struct gdbarch *gdbarch,
          int size;
 
          insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err);
-         size = (err != 0
-                 ? 2 : (mips_insn_size (ISA_MICROMIPS, insn) == 2
-                        ? 2 : 4));
+         size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn);
          *pcptr = unmake_compact_addr (pc);
          *lenptr = size;
          return (size == 2) ? micromips16_little_breakpoint
@@ -7376,12 +7328,14 @@ micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
 {
   ULONGEST insn;
   int status;
+  int size;
 
   insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
   if (status)
     return 0;
+  size = mips_insn_size (ISA_MICROMIPS, insn);
   insn <<= 16;
-  if (mips_insn_size (ISA_MICROMIPS, insn) == 2 * MIPS_INSN16_SIZE)
+  if (size == 2 * MIPS_INSN16_SIZE)
     {
       insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
       if (status)
@@ -8460,7 +8414,8 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
          /* On Irix, ELF64 executables use the N64 ABI.  The
             pseudo-sections which describe the ABI aren't present
             on IRIX.  (Even for executables created by gcc.)  */
-         if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
+         if (info.abfd != NULL
+             && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
              && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
            found_abi = MIPS_ABI_N64;
          else