/* PPC GNU/Linux native support.
- Copyright (C) 1988-2020 Free Software Foundation, Inc.
+ Copyright (C) 1988-2021 Free Software Foundation, Inc.
This file is part of GDB.
struct ppc_debug_info
{
- uint32_t version; /* Only version 1 exists to date. */
- uint32_t num_instruction_bps;
- uint32_t num_data_bps;
- uint32_t num_condition_regs;
- uint32_t data_bp_alignment;
- uint32_t sizeof_condition; /* size of the DVC register. */
- uint64_t features;
+ uint32_t version; /* Only version 1 exists to date. */
+ uint32_t num_instruction_bps;
+ uint32_t num_data_bps;
+ uint32_t num_condition_regs;
+ uint32_t data_bp_alignment;
+ uint32_t sizeof_condition; /* size of the DVC register. */
+ uint64_t features;
};
/* Features will have bits indicating whether there is support for: */
struct ppc_hw_breakpoint
{
- uint32_t version; /* currently, version must be 1 */
- uint32_t trigger_type; /* only some combinations allowed */
- uint32_t addr_mode; /* address match mode */
- uint32_t condition_mode; /* break/watchpoint condition flags */
- uint64_t addr; /* break/watchpoint address */
- uint64_t addr2; /* range end or mask */
- uint64_t condition_value; /* contents of the DVC register */
+ uint32_t version; /* currently, version must be 1 */
+ uint32_t trigger_type; /* only some combinations allowed */
+ uint32_t addr_mode; /* address match mode */
+ uint32_t condition_mode; /* break/watchpoint condition flags */
+ uint64_t addr; /* break/watchpoint address */
+ uint64_t addr2; /* range end or mask */
+ uint64_t condition_value; /* contents of the DVC register */
};
/* Trigger type. */
#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
#define PPC_BREAKPOINT_CONDITION_BE(n) \
- (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
+ (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
#endif /* PPC_PTRACE_GETHWDBGINFO */
/* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
#define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
#endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
+/* Feature defined on Linux kernel v5.1: Second watchpoint support. */
+#ifndef PPC_DEBUG_FEATURE_DATA_BP_ARCH_31
+#define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 0x20
+#endif /* PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 */
+
/* The version of the PowerPC HWDEBUG kernel interface that we will use, if
available. */
#define PPC_DEBUG_CURRENT_VERSION 1
/* This is the layout of the POWER7 VSX registers and the way they overlap
with the existing FPR and VMX registers.
- VSR doubleword 0 VSR doubleword 1
- ----------------------------------------------------------------
+ VSR doubleword 0 VSR doubleword 1
+ ----------------------------------------------------------------
VSR[0] | FPR[0] | |
- ----------------------------------------------------------------
+ ----------------------------------------------------------------
VSR[1] | FPR[1] | |
- ----------------------------------------------------------------
- | ... | |
- | ... | |
- ----------------------------------------------------------------
+ ----------------------------------------------------------------
+ | ... | |
+ | ... | |
+ ----------------------------------------------------------------
VSR[30] | FPR[30] | |
- ----------------------------------------------------------------
+ ----------------------------------------------------------------
VSR[31] | FPR[31] | |
- ----------------------------------------------------------------
+ ----------------------------------------------------------------
VSR[32] | VR[0] |
- ----------------------------------------------------------------
+ ----------------------------------------------------------------
VSR[33] | VR[1] |
- ----------------------------------------------------------------
- | ... |
- | ... |
- ----------------------------------------------------------------
+ ----------------------------------------------------------------
+ | ... |
+ | ... |
+ ----------------------------------------------------------------
VSR[62] | VR[30] |
- ----------------------------------------------------------------
+ ----------------------------------------------------------------
VSR[63] | VR[31] |
- ----------------------------------------------------------------
+ ----------------------------------------------------------------
VSX has 64 128bit registers. The first 32 registers overlap with
the FP registers (doubleword 0) and hence extend them with additional
bool no_features = false;
if (ptrace (PPC_PTRACE_GETHWDBGINFO, ptid.lwp (), 0, &m_hwdebug_info)
- != -1)
+ >= 0)
{
/* If there are no advertised features, we don't use the
HWDEBUG interface and try the DEBUGREG interface instead.
{
unsigned long wp;
- if (ptrace (PTRACE_GET_DEBUGREG, ptid.lwp (), 0, &wp) != -1)
+ if (ptrace (PTRACE_GET_DEBUGREG, ptid.lwp (), 0, &wp) >= 0)
{
m_interface.emplace (DEBUGREG);
return;
if (ret < 0)
{
if (errno == EIO)
- {
- have_ptrace_getvrregs = 0;
- return;
- }
+ {
+ have_ptrace_getvrregs = 0;
+ return;
+ }
perror_with_name (_("Unable to fetch AltiVec registers"));
}
if (have_ptrace_getsetevrregs)
{
if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
- return;
+ return;
else
- {
- /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
- we just return zeros. */
- if (errno == EIO)
- have_ptrace_getsetevrregs = 0;
- else
- /* Anything else needs to be reported. */
- perror_with_name (_("Unable to fetch SPE registers"));
- }
+ {
+ /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
+ we just return zeros. */
+ if (errno == EIO)
+ have_ptrace_getsetevrregs = 0;
+ else
+ /* Anything else needs to be reported. */
+ perror_with_name (_("Unable to fetch SPE registers"));
+ }
}
memset (evrregset, 0, sizeof (*evrregset));
struct gdb_evrregset_t evrregs;
gdb_assert (sizeof (evrregs.evr[0])
- == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
+ == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
gdb_assert (sizeof (evrregs.acc)
- == register_size (gdbarch, tdep->ppc_acc_regnum));
+ == register_size (gdbarch, tdep->ppc_acc_regnum));
gdb_assert (sizeof (evrregs.spefscr)
- == register_size (gdbarch, tdep->ppc_spefscr_regnum));
+ == register_size (gdbarch, tdep->ppc_spefscr_regnum));
get_spe_registers (tid, &evrregs);
int i;
for (i = 0; i < ppc_num_gprs; i++)
- regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]);
+ regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]);
}
else if (tdep->ppc_ev0_upper_regnum <= regno
- && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
+ && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
regcache->raw_supply (regno,
&evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
if (altivec_register_p (gdbarch, regno))
{
/* If this is the first time through, or if it is not the first
- time through, and we have confirmed that there is kernel
- support for such a ptrace request, then go and fetch the
- register. */
+ time through, and we have confirmed that there is kernel
+ support for such a ptrace request, then go and fetch the
+ register. */
if (have_ptrace_getvrregs)
{
- fetch_altivec_registers (regcache, tid, regno);
- return;
+ fetch_altivec_registers (regcache, tid, regno);
+ return;
}
/* If we have discovered that there is no ptrace support for
- AltiVec registers, fall through and return zeroes, because
- regaddr will be -1 in this case. */
+ AltiVec registers, fall through and return zeroes, because
+ regaddr will be -1 in this case. */
}
else if (vsx_register_p (gdbarch, regno))
{
regaddr += sizeof (long);
if (errno != 0)
{
- char message[128];
+ char message[128];
xsnprintf (message, sizeof (message), "reading register %s (#%d)",
gdbarch_register_name (gdbarch, regno), regno);
perror_with_name (message);
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
{
/* Little-endian values are always found at the left end of the
- bytes transferred. */
+ bytes transferred. */
regcache->raw_supply (regno, buf);
}
else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
/* Big-endian values are found at the right end of the bytes
- transferred. */
+ transferred. */
size_t padding = (bytes_transferred - register_size (gdbarch, regno));
regcache->raw_supply (regno, buf + padding);
}
else
internal_error (__FILE__, __LINE__,
- _("fetch_register: unexpected byte order: %d"),
- gdbarch_byte_order (gdbarch));
+ _("fetch_register: unexpected byte order: %d"),
+ gdbarch_byte_order (gdbarch));
}
/* This function actually issues the request to ptrace, telling
if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
{
if (errno == EIO)
- {
- have_ptrace_getsetregs = 0;
- return 0;
- }
+ {
+ have_ptrace_getsetregs = 0;
+ return 0;
+ }
perror_with_name (_("Couldn't get general-purpose registers."));
}
if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
{
if (errno == EIO)
- {
- have_ptrace_getsetfpregs = 0;
- return 0;
- }
+ {
+ have_ptrace_getsetfpregs = 0;
+ return 0;
+ }
perror_with_name (_("Couldn't get floating-point registers."));
}
if (ret < 0)
{
if (errno == EIO)
- {
- have_ptrace_getvrregs = 0;
- return;
- }
+ {
+ have_ptrace_getvrregs = 0;
+ return;
+ }
perror_with_name (_("Unable to fetch AltiVec registers"));
}
if (have_ptrace_getsetevrregs)
{
if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
- return;
+ return;
else
- {
- /* EIO means that the PTRACE_SETEVRREGS request isn't
- supported; we fail silently, and don't try the call
- again. */
- if (errno == EIO)
- have_ptrace_getsetevrregs = 0;
- else
- /* Anything else needs to be reported. */
- perror_with_name (_("Unable to set SPE registers"));
- }
+ {
+ /* EIO means that the PTRACE_SETEVRREGS request isn't
+ supported; we fail silently, and don't try the call
+ again. */
+ if (errno == EIO)
+ have_ptrace_getsetevrregs = 0;
+ else
+ /* Anything else needs to be reported. */
+ perror_with_name (_("Unable to set SPE registers"));
+ }
}
}
struct gdb_evrregset_t evrregs;
gdb_assert (sizeof (evrregs.evr[0])
- == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
+ == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
gdb_assert (sizeof (evrregs.acc)
- == register_size (gdbarch, tdep->ppc_acc_regnum));
+ == register_size (gdbarch, tdep->ppc_acc_regnum));
gdb_assert (sizeof (evrregs.spefscr)
- == register_size (gdbarch, tdep->ppc_spefscr_regnum));
+ == register_size (gdbarch, tdep->ppc_spefscr_regnum));
if (regno == -1)
/* Since we're going to write out every register, the code below
&evrregs.evr[i]);
}
else if (tdep->ppc_ev0_upper_regnum <= regno
- && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
+ && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
regcache->raw_collect (regno,
&evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
regaddr += sizeof (long);
if (errno == EIO
- && (regno == tdep->ppc_fpscr_regnum
+ && (regno == tdep->ppc_fpscr_regnum
|| regno == PPC_ORIG_R3_REGNUM
|| regno == PPC_TRAP_REGNUM))
{
if (errno != 0)
{
- char message[128];
+ char message[128];
xsnprintf (message, sizeof (message), "writing register %s (#%d)",
gdbarch_register_name (gdbarch, regno), regno);
perror_with_name (message);
if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
{
if (errno == EIO)
- {
- have_ptrace_getsetregs = 0;
- return 0;
- }
+ {
+ have_ptrace_getsetregs = 0;
+ return 0;
+ }
perror_with_name (_("Couldn't get general-purpose registers."));
}
if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
{
if (errno == EIO)
- {
- have_ptrace_getsetregs = 0;
- return 0;
- }
+ {
+ have_ptrace_getsetregs = 0;
+ return 0;
+ }
perror_with_name (_("Couldn't set general-purpose registers."));
}
if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
{
if (errno == EIO)
- {
- have_ptrace_getsetfpregs = 0;
- return 0;
- }
+ {
+ have_ptrace_getsetfpregs = 0;
+ return 0;
+ }
perror_with_name (_("Couldn't get floating-point registers."));
}
if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
{
if (errno == EIO)
- {
- have_ptrace_getsetfpregs = 0;
- return 0;
- }
+ {
+ have_ptrace_getsetfpregs = 0;
+ return 0;
+ }
perror_with_name (_("Couldn't set floating-point registers."));
}
struct gdb_evrregset_t evrregset;
if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
- return tdesc_powerpc_e500l;
+ return tdesc_powerpc_e500l;
/* EIO means that the PTRACE_GETEVRREGS request isn't supported.
Anything else needs to be reported. */
gdb_vrregset_t vrregset;
if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
- features.altivec = true;
+ features.altivec = true;
/* EIO means that the PTRACE_GETVRREGS request isn't supported.
Anything else needs to be reported. */
watchpoints. */
if (m_dreg_interface.hwdebug_p ())
{
- int region_size;
const struct ppc_debug_info &hwdebug_info = (m_dreg_interface
.hwdebug_info ());
+ int region_size = hwdebug_info.data_bp_alignment;
+ int region_align = region_size;
/* Embedded DAC-based processors, like the PowerPC 440 have ranged
watchpoints and can watch any access within an arbitrary memory
region. This is useful to watch arrays and structs, for instance. It
- takes two hardware watchpoints though. */
+ takes two hardware watchpoints though. */
if (len > 1
&& hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE
&& linux_get_hwcap (current_top_target ()) & PPC_FEATURE_BOOKE)
return 2;
/* Check if the processor provides DAWR interface. */
if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR)
- /* DAWR interface allows to watch up to 512 byte wide ranges which
- can't cross a 512 byte boundary. */
- region_size = 512;
- else
- region_size = hwdebug_info.data_bp_alignment;
+ {
+ /* DAWR interface allows to watch up to 512 byte wide ranges. */
+ region_size = 512;
+ /* DAWR interface allows to watch up to 512 byte wide ranges which
+ can't cross a 512 byte bondary on machines that doesn't have a
+ second DAWR (P9 or less). */
+ if (!(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_ARCH_31))
+ region_align = 512;
+ }
/* Server processors provide one hardware watchpoint and addr+len should
- fall in the watchable region provided by the ptrace interface. */
- if (region_size
- && (addr + len > (addr & ~(region_size - 1)) + region_size))
+ fall in the watchable region provided by the ptrace interface. */
+ if (region_align
+ && (addr + len > (addr & ~(region_align - 1)) + region_size))
return 0;
}
/* addr+len must fall in the 8 byte watchable region for DABR-based
if (cond->elts[0].opcode != BINOP_EQUAL)
return 0;
- fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
+ fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, false);
num_accesses_left = num_memory_accesses (left_chain);
if (left_val == NULL || num_accesses_left < 0)
return 0;
- fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
+ fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, false);
num_accesses_right = num_memory_accesses (right_chain);
if (right_val == NULL || num_accesses_right < 0)
the debug register state when fork and clone events are
detected. */
if (ptrace (PPC_PTRACE_DELHWDEBUG, lp->ptid.lwp (), 0,
- bp_it->first) == -1)
+ bp_it->first) < 0)
if (errno != ENOENT)
perror_with_name (_("Error deleting hardware "
"breakpoint or watchpoint"));
{
gdb_assert (m_dreg_interface.debugreg_p ());
- /* Passing 0 to PTRACE_SET_DEBUGREG will clear the
- watchpoint. */
- long wp = 0;
+ /* Passing 0 to PTRACE_SET_DEBUGREG will clear the watchpoint. We
+ always clear the watchpoint instead of just overwriting it, in
+ case there is a request for a new watchpoint, because on some
+ older kernel versions and configurations simply overwriting the
+ watchpoint after it was hit would not re-enable it. */
+ if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, 0) < 0)
+ perror_with_name (_("Error clearing hardware watchpoint"));
/* GDB requested a watchpoint to be installed. */
if (process_it != m_process_info.end ()
&& process_it->second.requested_wp_val.has_value ())
- wp = *(process_it->second.requested_wp_val);
-
- long ret = ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (),
- 0, wp);
+ {
+ long wp = *(process_it->second.requested_wp_val);
- if (ret == -1)
- perror_with_name (_("Error setting hardware watchpoint"));
+ if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, wp) < 0)
+ perror_with_name (_("Error setting hardware watchpoint"));
+ }
}
lp_arch_info->debug_regs_stale = false;
projects / deliverable / binutils-gdb.git / blobdiff