/* PPC GNU/Linux native support.
- Copyright 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002,
- 2003 Free Software Foundation, Inc.
+ Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,
+ 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "gdb_string.h"
#include "inferior.h"
#include "gdbcore.h"
#include "regcache.h"
+#include "gdb_assert.h"
+#include "target.h"
+#include "linux-nat.h"
+#include <stdint.h>
#include <sys/types.h>
#include <sys/param.h>
#include <signal.h>
/* Prototypes for supply_gregset etc. */
#include "gregset.h"
#include "ppc-tdep.h"
+#include "ppc-linux-tdep.h"
-#ifndef PT_READ_U
-#define PT_READ_U PTRACE_PEEKUSR
+/* This sometimes isn't defined. */
+#ifndef PT_ORIG_R3
+#define PT_ORIG_R3 34
#endif
-#ifndef PT_WRITE_U
-#define PT_WRITE_U PTRACE_POKEUSR
-#endif
-
-/* Default the type of the ptrace transfer to int. */
-#ifndef PTRACE_XFER_TYPE
-#define PTRACE_XFER_TYPE int
+#ifndef PT_TRAP
+#define PT_TRAP 40
#endif
/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
#define PTRACE_SETVRREGS 19
#endif
+
+/* Similarly for the ptrace requests for getting / setting the SPE
+ registers (ev0 -- ev31, acc, and spefscr). See the description of
+ gdb_evrregset_t for details. */
+#ifndef PTRACE_GETEVRREGS
+#define PTRACE_GETEVRREGS 20
+#define PTRACE_SETEVRREGS 21
+#endif
+
+/* Similarly for the hardware watchpoint support. */
+#ifndef PTRACE_GET_DEBUGREG
+#define PTRACE_GET_DEBUGREG 25
+#endif
+#ifndef PTRACE_SET_DEBUGREG
+#define PTRACE_SET_DEBUGREG 26
+#endif
+#ifndef PTRACE_GETSIGINFO
+#define PTRACE_GETSIGINFO 0x4202
+#endif
+
/* This oddity is because the Linux kernel defines elf_vrregset_t as
an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
typedef char gdb_vrregset_t[SIZEOF_VRREGS];
-/* For runtime check of ptrace support for VRREGS. */
-int have_ptrace_getvrregs = 1;
-int
-kernel_u_size (void)
+/* On PPC processors that support the the Signal Processing Extension
+ (SPE) APU, the general-purpose registers are 64 bits long.
+ However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
+ ptrace calls only access the lower half of each register, to allow
+ them to behave the same way they do on non-SPE systems. There's a
+ separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
+ read and write the top halves of all the general-purpose registers
+ at once, along with some SPE-specific registers.
+
+ GDB itself continues to claim the general-purpose registers are 32
+ bits long. It has unnamed raw registers that hold the upper halves
+ of the gprs, and the the full 64-bit SIMD views of the registers,
+ 'ev0' -- 'ev31', are pseudo-registers that splice the top and
+ bottom halves together.
+
+ This is the structure filled in by PTRACE_GETEVRREGS and written to
+ the inferior's registers by PTRACE_SETEVRREGS. */
+struct gdb_evrregset_t
{
- return (sizeof (struct user));
-}
+ unsigned long evr[32];
+ unsigned long long acc;
+ unsigned long spefscr;
+};
+
+
+/* Non-zero if our kernel may support the PTRACE_GETVRREGS and
+ PTRACE_SETVRREGS requests, for reading and writing the Altivec
+ registers. Zero if we've tried one of them and gotten an
+ error. */
+int have_ptrace_getvrregs = 1;
+
+/* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
+ PTRACE_SETEVRREGS requests, for reading and writing the SPE
+ registers. Zero if we've tried one of them and gotten an
+ error. */
+int have_ptrace_getsetevrregs = 1;
/* *INDENT-OFF* */
/* registers layout, as presented by the ptrace interface:
/* *INDENT_ON * */
static int
-ppc_register_u_addr (int regno)
+ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
{
int u_addr = -1;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
- int wordsize = tdep->wordsize;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
+ interface, and not the wordsize of the program's ABI. */
+ int wordsize = sizeof (long);
/* General purpose registers occupy 1 slot each in the buffer */
- if (regno >= tdep->ppc_gp0_regnum && regno <= tdep->ppc_gplast_regnum )
- u_addr = ((PT_R0 + regno) * wordsize);
+ if (regno >= tdep->ppc_gp0_regnum
+ && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
+ u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
/* Floating point regs: eight bytes each in both 32- and 64-bit
ptrace interfaces. Thus, two slots each in 32-bit interface, one
slot each in 64-bit interface. */
- if (regno >= FP0_REGNUM && regno <= FPLAST_REGNUM)
- u_addr = (PT_FPR0 * wordsize) + ((regno - FP0_REGNUM) * 8);
+ if (tdep->ppc_fp0_regnum >= 0
+ && regno >= tdep->ppc_fp0_regnum
+ && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
+ u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
/* UISA special purpose registers: 1 slot each */
- if (regno == PC_REGNUM)
+ if (regno == gdbarch_pc_regnum (gdbarch))
u_addr = PT_NIP * wordsize;
if (regno == tdep->ppc_lr_regnum)
u_addr = PT_LNK * wordsize;
#endif
if (regno == tdep->ppc_ps_regnum)
u_addr = PT_MSR * wordsize;
- if (regno == tdep->ppc_fpscr_regnum)
- u_addr = PT_FPSCR * wordsize;
-
+ if (regno == PPC_ORIG_R3_REGNUM)
+ u_addr = PT_ORIG_R3 * wordsize;
+ if (regno == PPC_TRAP_REGNUM)
+ u_addr = PT_TRAP * wordsize;
+ if (tdep->ppc_fpscr_regnum >= 0
+ && regno == tdep->ppc_fpscr_regnum)
+ {
+ /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
+ kernel headers incorrectly contained the 32-bit definition of
+ PT_FPSCR. For the 32-bit definition, floating-point
+ registers occupy two 32-bit "slots", and the FPSCR lives in
+ the secondhalf of such a slot-pair (hence +1). For 64-bit,
+ the FPSCR instead occupies the full 64-bit 2-word-slot and
+ hence no adjustment is necessary. Hack around this. */
+ if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
+ u_addr = (48 + 32) * wordsize;
+ else
+ u_addr = PT_FPSCR * wordsize;
+ }
return u_addr;
}
-static int
-ppc_ptrace_cannot_fetch_store_register (int regno)
-{
- return (ppc_register_u_addr (regno) == -1);
-}
-
/* The Linux kernel ptrace interface for AltiVec registers uses the
registers set mechanism, as opposed to the interface for all the
other registers, that stores/fetches each register individually. */
static void
-fetch_altivec_register (int tid, int regno)
+fetch_altivec_register (struct regcache *regcache, int tid, int regno)
{
int ret;
int offset = 0;
gdb_vrregset_t regs;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
- int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
if (ret < 0)
have_ptrace_getvrregs = 0;
return;
}
- perror_with_name ("Unable to fetch AltiVec register");
+ perror_with_name (_("Unable to fetch AltiVec register"));
}
/* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
vector. VRSAVE is at the end of the array in a 4 bytes slot, so
there is no need to define an offset for it. */
if (regno == (tdep->ppc_vrsave_regnum - 1))
- offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum);
+ offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
- supply_register (regno,
- regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
+ regcache_raw_supply (regcache, regno,
+ regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
}
+/* Fetch the top 32 bits of TID's general-purpose registers and the
+ SPE-specific registers, and place the results in EVRREGSET. If we
+ don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
+ zeros.
+
+ All the logic to deal with whether or not the PTRACE_GETEVRREGS and
+ PTRACE_SETEVRREGS requests are supported is isolated here, and in
+ set_spe_registers. */
+static void
+get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
+{
+ if (have_ptrace_getsetevrregs)
+ {
+ if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
+ return;
+ else
+ {
+ /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
+ we just return zeros. */
+ if (errno == EIO)
+ have_ptrace_getsetevrregs = 0;
+ else
+ /* Anything else needs to be reported. */
+ perror_with_name (_("Unable to fetch SPE registers"));
+ }
+ }
+
+ memset (evrregset, 0, sizeof (*evrregset));
+}
+
+/* Supply values from TID for SPE-specific raw registers: the upper
+ halves of the GPRs, the accumulator, and the spefscr. REGNO must
+ be the number of an upper half register, acc, spefscr, or -1 to
+ supply the values of all registers. */
static void
-fetch_register (int tid, int regno)
+fetch_spe_register (struct regcache *regcache, int tid, int regno)
{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ struct gdb_evrregset_t evrregs;
+
+ gdb_assert (sizeof (evrregs.evr[0])
+ == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
+ gdb_assert (sizeof (evrregs.acc)
+ == register_size (gdbarch, tdep->ppc_acc_regnum));
+ gdb_assert (sizeof (evrregs.spefscr)
+ == register_size (gdbarch, tdep->ppc_spefscr_regnum));
+
+ get_spe_registers (tid, &evrregs);
+
+ if (regno == -1)
+ {
+ int i;
+
+ for (i = 0; i < ppc_num_gprs; i++)
+ regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
+ &evrregs.evr[i]);
+ }
+ else if (tdep->ppc_ev0_upper_regnum <= regno
+ && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
+ regcache_raw_supply (regcache, regno,
+ &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
+
+ if (regno == -1
+ || regno == tdep->ppc_acc_regnum)
+ regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
+
+ if (regno == -1
+ || regno == tdep->ppc_spefscr_regnum)
+ regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
+ &evrregs.spefscr);
+}
+
+static void
+fetch_register (struct regcache *regcache, int tid, int regno)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* This isn't really an address. But ptrace thinks of it as one. */
- char mess[128]; /* For messages */
- int i;
+ CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
+ int bytes_transferred;
unsigned int offset; /* Offset of registers within the u area. */
char buf[MAX_REGISTER_SIZE];
- CORE_ADDR regaddr = ppc_register_u_addr (regno);
- if (altivec_register_p (regno))
+ if (altivec_register_p (gdbarch, regno))
{
/* If this is the first time through, or if it is not the first
time through, and we have comfirmed that there is kernel
register. */
if (have_ptrace_getvrregs)
{
- fetch_altivec_register (tid, regno);
+ fetch_altivec_register (regcache, tid, regno);
return;
}
/* If we have discovered that there is no ptrace support for
AltiVec registers, fall through and return zeroes, because
regaddr will be -1 in this case. */
}
+ else if (spe_register_p (gdbarch, regno))
+ {
+ fetch_spe_register (regcache, tid, regno);
+ return;
+ }
if (regaddr == -1)
{
- memset (buf, '\0', DEPRECATED_REGISTER_RAW_SIZE (regno)); /* Supply zeroes */
- supply_register (regno, buf);
+ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
+ regcache_raw_supply (regcache, regno, buf);
return;
}
- for (i = 0; i < DEPRECATED_REGISTER_RAW_SIZE (regno); i += sizeof (PTRACE_XFER_TYPE))
+ /* Read the raw register using sizeof(long) sized chunks. On a
+ 32-bit platform, 64-bit floating-point registers will require two
+ transfers. */
+ for (bytes_transferred = 0;
+ bytes_transferred < register_size (gdbarch, regno);
+ bytes_transferred += sizeof (long))
{
errno = 0;
- *(PTRACE_XFER_TYPE *) & buf[i] = ptrace (PT_READ_U, tid,
- (PTRACE_ARG3_TYPE) regaddr, 0);
- regaddr += sizeof (PTRACE_XFER_TYPE);
+ *(long *) &buf[bytes_transferred]
+ = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
+ regaddr += sizeof (long);
if (errno != 0)
{
- sprintf (mess, "reading register %s (#%d)",
- REGISTER_NAME (regno), regno);
- perror_with_name (mess);
+ char message[128];
+ sprintf (message, "reading register %s (#%d)",
+ gdbarch_register_name (gdbarch, regno), regno);
+ perror_with_name (message);
}
}
- supply_register (regno, buf);
+
+ /* Now supply the register. Keep in mind that the regcache's idea
+ of the register's size may not be a multiple of sizeof
+ (long). */
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
+ {
+ /* Little-endian values are always found at the left end of the
+ bytes transferred. */
+ regcache_raw_supply (regcache, regno, buf);
+ }
+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ {
+ /* Big-endian values are found at the right end of the bytes
+ transferred. */
+ size_t padding = (bytes_transferred - register_size (gdbarch, regno));
+ regcache_raw_supply (regcache, regno, buf + padding);
+ }
+ else
+ internal_error (__FILE__, __LINE__,
+ _("fetch_register: unexpected byte order: %d"),
+ gdbarch_byte_order (gdbarch));
}
static void
-supply_vrregset (gdb_vrregset_t *vrregsetp)
+supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)
{
int i;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
- int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
- int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum);
+ int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
+ int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
for (i = 0; i < num_of_vrregs; i++)
{
occupies a whole vector, while VRSAVE occupies a full 4 bytes
slot. */
if (i == (num_of_vrregs - 2))
- supply_register (tdep->ppc_vr0_regnum + i,
- *vrregsetp + i * vrregsize + offset);
+ regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
+ *vrregsetp + i * vrregsize + offset);
else
- supply_register (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize);
+ regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
+ *vrregsetp + i * vrregsize);
}
}
static void
-fetch_altivec_registers (int tid)
+fetch_altivec_registers (struct regcache *regcache, int tid)
{
int ret;
gdb_vrregset_t regs;
have_ptrace_getvrregs = 0;
return;
}
- perror_with_name ("Unable to fetch AltiVec registers");
+ perror_with_name (_("Unable to fetch AltiVec registers"));
}
- supply_vrregset (®s);
+ supply_vrregset (regcache, ®s);
}
static void
-fetch_ppc_registers (int tid)
+fetch_ppc_registers (struct regcache *regcache, int tid)
{
int i;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- for (i = 0; i <= tdep->ppc_fpscr_regnum; i++)
- fetch_register (tid, i);
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ for (i = 0; i < ppc_num_gprs; i++)
+ fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
+ if (tdep->ppc_fp0_regnum >= 0)
+ for (i = 0; i < ppc_num_fprs; i++)
+ fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
+ fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
+ if (tdep->ppc_ps_regnum != -1)
+ fetch_register (regcache, tid, tdep->ppc_ps_regnum);
+ if (tdep->ppc_cr_regnum != -1)
+ fetch_register (regcache, tid, tdep->ppc_cr_regnum);
+ if (tdep->ppc_lr_regnum != -1)
+ fetch_register (regcache, tid, tdep->ppc_lr_regnum);
+ if (tdep->ppc_ctr_regnum != -1)
+ fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
+ if (tdep->ppc_xer_regnum != -1)
+ fetch_register (regcache, tid, tdep->ppc_xer_regnum);
if (tdep->ppc_mq_regnum != -1)
- fetch_register (tid, tdep->ppc_mq_regnum);
+ fetch_register (regcache, tid, tdep->ppc_mq_regnum);
+ if (ppc_linux_trap_reg_p (gdbarch))
+ {
+ fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
+ fetch_register (regcache, tid, PPC_TRAP_REGNUM);
+ }
+ if (tdep->ppc_fpscr_regnum != -1)
+ fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
if (have_ptrace_getvrregs)
if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
- fetch_altivec_registers (tid);
+ fetch_altivec_registers (regcache, tid);
+ if (tdep->ppc_ev0_upper_regnum >= 0)
+ fetch_spe_register (regcache, tid, -1);
}
/* Fetch registers from the child process. Fetch all registers if
regno == -1, otherwise fetch all general registers or all floating
point registers depending upon the value of regno. */
-void
-fetch_inferior_registers (int regno)
+static void
+ppc_linux_fetch_inferior_registers (struct regcache *regcache, int regno)
{
/* Overload thread id onto process id */
int tid = TIDGET (inferior_ptid);
tid = PIDGET (inferior_ptid);
if (regno == -1)
- fetch_ppc_registers (tid);
+ fetch_ppc_registers (regcache, tid);
else
- fetch_register (tid, regno);
+ fetch_register (regcache, tid, regno);
}
/* Store one register. */
static void
-store_altivec_register (int tid, int regno)
+store_altivec_register (const struct regcache *regcache, int tid, int regno)
{
int ret;
int offset = 0;
gdb_vrregset_t regs;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
- int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s);
if (ret < 0)
have_ptrace_getvrregs = 0;
return;
}
- perror_with_name ("Unable to fetch AltiVec register");
+ perror_with_name (_("Unable to fetch AltiVec register"));
}
/* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
long on the hardware. */
if (regno == (tdep->ppc_vrsave_regnum - 1))
- offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum);
+ offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
- regcache_collect (regno,
- regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
+ regcache_raw_collect (regcache, regno,
+ regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s);
if (ret < 0)
- perror_with_name ("Unable to store AltiVec register");
+ perror_with_name (_("Unable to store AltiVec register"));
}
+/* Assuming TID referrs to an SPE process, set the top halves of TID's
+ general-purpose registers and its SPE-specific registers to the
+ values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
+ nothing.
+
+ All the logic to deal with whether or not the PTRACE_GETEVRREGS and
+ PTRACE_SETEVRREGS requests are supported is isolated here, and in
+ get_spe_registers. */
static void
-store_register (int tid, int regno)
+set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
{
+ if (have_ptrace_getsetevrregs)
+ {
+ if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
+ return;
+ else
+ {
+ /* EIO means that the PTRACE_SETEVRREGS request isn't
+ supported; we fail silently, and don't try the call
+ again. */
+ if (errno == EIO)
+ have_ptrace_getsetevrregs = 0;
+ else
+ /* Anything else needs to be reported. */
+ perror_with_name (_("Unable to set SPE registers"));
+ }
+ }
+}
+
+/* Write GDB's value for the SPE-specific raw register REGNO to TID.
+ If REGNO is -1, write the values of all the SPE-specific
+ registers. */
+static void
+store_spe_register (const struct regcache *regcache, int tid, int regno)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ struct gdb_evrregset_t evrregs;
+
+ gdb_assert (sizeof (evrregs.evr[0])
+ == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
+ gdb_assert (sizeof (evrregs.acc)
+ == register_size (gdbarch, tdep->ppc_acc_regnum));
+ gdb_assert (sizeof (evrregs.spefscr)
+ == register_size (gdbarch, tdep->ppc_spefscr_regnum));
+
+ if (regno == -1)
+ /* Since we're going to write out every register, the code below
+ should store to every field of evrregs; if that doesn't happen,
+ make it obvious by initializing it with suspicious values. */
+ memset (&evrregs, 42, sizeof (evrregs));
+ else
+ /* We can only read and write the entire EVR register set at a
+ time, so to write just a single register, we do a
+ read-modify-write maneuver. */
+ get_spe_registers (tid, &evrregs);
+
+ if (regno == -1)
+ {
+ int i;
+
+ for (i = 0; i < ppc_num_gprs; i++)
+ regcache_raw_collect (regcache,
+ tdep->ppc_ev0_upper_regnum + i,
+ &evrregs.evr[i]);
+ }
+ else if (tdep->ppc_ev0_upper_regnum <= regno
+ && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
+ regcache_raw_collect (regcache, regno,
+ &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
+
+ if (regno == -1
+ || regno == tdep->ppc_acc_regnum)
+ regcache_raw_collect (regcache,
+ tdep->ppc_acc_regnum,
+ &evrregs.acc);
+
+ if (regno == -1
+ || regno == tdep->ppc_spefscr_regnum)
+ regcache_raw_collect (regcache,
+ tdep->ppc_spefscr_regnum,
+ &evrregs.spefscr);
+
+ /* Write back the modified register set. */
+ set_spe_registers (tid, &evrregs);
+}
+
+static void
+store_register (const struct regcache *regcache, int tid, int regno)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* This isn't really an address. But ptrace thinks of it as one. */
- CORE_ADDR regaddr = ppc_register_u_addr (regno);
- char mess[128]; /* For messages */
+ CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
int i;
- unsigned int offset; /* Offset of registers within the u area. */
+ size_t bytes_to_transfer;
char buf[MAX_REGISTER_SIZE];
- if (altivec_register_p (regno))
+ if (altivec_register_p (gdbarch, regno))
+ {
+ store_altivec_register (regcache, tid, regno);
+ return;
+ }
+ else if (spe_register_p (gdbarch, regno))
{
- store_altivec_register (tid, regno);
+ store_spe_register (regcache, tid, regno);
return;
}
if (regaddr == -1)
return;
- regcache_collect (regno, buf);
- for (i = 0; i < DEPRECATED_REGISTER_RAW_SIZE (regno); i += sizeof (PTRACE_XFER_TYPE))
+ /* First collect the register. Keep in mind that the regcache's
+ idea of the register's size may not be a multiple of sizeof
+ (long). */
+ memset (buf, 0, sizeof buf);
+ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
+ {
+ /* Little-endian values always sit at the left end of the buffer. */
+ regcache_raw_collect (regcache, regno, buf);
+ }
+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ {
+ /* Big-endian values sit at the right end of the buffer. */
+ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
+ regcache_raw_collect (regcache, regno, buf + padding);
+ }
+
+ for (i = 0; i < bytes_to_transfer; i += sizeof (long))
{
errno = 0;
- ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) regaddr,
- *(PTRACE_XFER_TYPE *) & buf[i]);
- regaddr += sizeof (PTRACE_XFER_TYPE);
+ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr,
+ *(long *) &buf[i]);
+ regaddr += sizeof (long);
if (errno == EIO
- && regno == gdbarch_tdep (current_gdbarch)->ppc_fpscr_regnum)
+ && (regno == tdep->ppc_fpscr_regnum
+ || regno == PPC_ORIG_R3_REGNUM
+ || regno == PPC_TRAP_REGNUM))
{
- /* Some older kernel versions don't allow fpscr to be written. */
+ /* Some older kernel versions don't allow fpscr, orig_r3
+ or trap to be written. */
continue;
}
if (errno != 0)
{
- sprintf (mess, "writing register %s (#%d)",
- REGISTER_NAME (regno), regno);
- perror_with_name (mess);
+ char message[128];
+ sprintf (message, "writing register %s (#%d)",
+ gdbarch_register_name (gdbarch, regno), regno);
+ perror_with_name (message);
}
}
}
static void
-fill_vrregset (gdb_vrregset_t *vrregsetp)
+fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
{
int i;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
- int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
- int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum);
+ int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
+ int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
for (i = 0; i < num_of_vrregs; i++)
{
/* The last 2 registers of this set are only 32 bit long, not
128, but only VSCR is fetched as a 16 bytes quantity. */
if (i == (num_of_vrregs - 2))
- regcache_collect (tdep->ppc_vr0_regnum + i,
- *vrregsetp + i * vrregsize + offset);
+ regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
+ *vrregsetp + i * vrregsize + offset);
else
- regcache_collect (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize);
+ regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
+ *vrregsetp + i * vrregsize);
}
}
static void
-store_altivec_registers (int tid)
+store_altivec_registers (const struct regcache *regcache, int tid)
{
int ret;
gdb_vrregset_t regs;
have_ptrace_getvrregs = 0;
return;
}
- perror_with_name ("Couldn't get AltiVec registers");
+ perror_with_name (_("Couldn't get AltiVec registers"));
}
- fill_vrregset (®s);
+ fill_vrregset (regcache, ®s);
if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0)
- perror_with_name ("Couldn't write AltiVec registers");
+ perror_with_name (_("Couldn't write AltiVec registers"));
}
static void
-store_ppc_registers (int tid)
+store_ppc_registers (const struct regcache *regcache, int tid)
{
int i;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- for (i = 0; i <= tdep->ppc_fpscr_regnum; i++)
- store_register (tid, i);
+ for (i = 0; i < ppc_num_gprs; i++)
+ store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
+ if (tdep->ppc_fp0_regnum >= 0)
+ for (i = 0; i < ppc_num_fprs; i++)
+ store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
+ store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
+ if (tdep->ppc_ps_regnum != -1)
+ store_register (regcache, tid, tdep->ppc_ps_regnum);
+ if (tdep->ppc_cr_regnum != -1)
+ store_register (regcache, tid, tdep->ppc_cr_regnum);
+ if (tdep->ppc_lr_regnum != -1)
+ store_register (regcache, tid, tdep->ppc_lr_regnum);
+ if (tdep->ppc_ctr_regnum != -1)
+ store_register (regcache, tid, tdep->ppc_ctr_regnum);
+ if (tdep->ppc_xer_regnum != -1)
+ store_register (regcache, tid, tdep->ppc_xer_regnum);
if (tdep->ppc_mq_regnum != -1)
- store_register (tid, tdep->ppc_mq_regnum);
+ store_register (regcache, tid, tdep->ppc_mq_regnum);
+ if (tdep->ppc_fpscr_regnum != -1)
+ store_register (regcache, tid, tdep->ppc_fpscr_regnum);
+ if (ppc_linux_trap_reg_p (gdbarch))
+ {
+ store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
+ store_register (regcache, tid, PPC_TRAP_REGNUM);
+ }
if (have_ptrace_getvrregs)
if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
- store_altivec_registers (tid);
+ store_altivec_registers (regcache, tid);
+ if (tdep->ppc_ev0_upper_regnum >= 0)
+ store_spe_register (regcache, tid, -1);
}
-void
-store_inferior_registers (int regno)
+static int
+ppc_linux_check_watch_resources (int type, int cnt, int ot)
+{
+ int tid;
+ ptid_t ptid = inferior_ptid;
+
+ /* DABR (data address breakpoint register) is optional for PPC variants.
+ Some variants have one DABR, others have none. So CNT can't be larger
+ than 1. */
+ if (cnt > 1)
+ return 0;
+
+ /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether
+ the target has DABR. If either answer is no, the ptrace call will
+ return -1. Fail in that case. */
+ tid = TIDGET (ptid);
+ if (tid == 0)
+ tid = PIDGET (ptid);
+
+ if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
+ return 0;
+ return 1;
+}
+
+static int
+ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
+{
+ /* Handle sub-8-byte quantities. */
+ if (len <= 0)
+ return 0;
+
+ /* addr+len must fall in the 8 byte watchable region. */
+ if ((addr + len) > (addr & ~7) + 8)
+ return 0;
+
+ return 1;
+}
+
+/* The cached DABR value, to install in new threads. */
+static long saved_dabr_value;
+
+/* Set a watchpoint of type TYPE at address ADDR. */
+static int
+ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw)
+{
+ struct lwp_info *lp;
+ ptid_t ptid;
+ long dabr_value;
+
+ dabr_value = addr & ~7;
+ switch (rw)
+ {
+ case hw_read:
+ /* Set read and translate bits. */
+ dabr_value |= 5;
+ break;
+ case hw_write:
+ /* Set write and translate bits. */
+ dabr_value |= 6;
+ break;
+ case hw_access:
+ /* Set read, write and translate bits. */
+ dabr_value |= 7;
+ break;
+ }
+
+ saved_dabr_value = dabr_value;
+
+ ALL_LWPS (lp, ptid)
+ if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0)
+ return -1;
+
+ return 0;
+}
+
+static int
+ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw)
+{
+ struct lwp_info *lp;
+ ptid_t ptid;
+ long dabr_value = 0;
+
+ saved_dabr_value = 0;
+ ALL_LWPS (lp, ptid)
+ if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0)
+ return -1;
+ return 0;
+}
+
+static void
+ppc_linux_new_thread (ptid_t ptid)
+{
+ ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value);
+}
+
+static int
+ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
+{
+ struct siginfo *siginfo_p;
+
+ siginfo_p = linux_nat_get_siginfo (inferior_ptid);
+
+ if (siginfo_p->si_signo != SIGTRAP
+ || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
+ return 0;
+
+ *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr;
+ return 1;
+}
+
+static int
+ppc_linux_stopped_by_watchpoint (void)
+{
+ CORE_ADDR addr;
+ return ppc_linux_stopped_data_address (¤t_target, &addr);
+}
+
+static int
+ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
+ CORE_ADDR addr,
+ CORE_ADDR start, int length)
+{
+ addr &= ~7;
+ /* Check whether [start, start+length-1] intersects [addr, addr+7]. */
+ return start <= addr + 7 && start + length - 1 >= addr;
+}
+
+static void
+ppc_linux_store_inferior_registers (struct regcache *regcache, int regno)
{
/* Overload thread id onto process id */
int tid = TIDGET (inferior_ptid);
tid = PIDGET (inferior_ptid);
if (regno >= 0)
- store_register (tid, regno);
+ store_register (regcache, tid, regno);
else
- store_ppc_registers (tid);
+ store_ppc_registers (regcache, tid);
}
+/* Functions for transferring registers between a gregset_t or fpregset_t
+ (see sys/ucontext.h) and gdb's regcache. The word size is that used
+ by the ptrace interface, not the current program's ABI. eg. If a
+ powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
+ read or write 64-bit gregsets. This is to suit the host libthread_db. */
+
void
-supply_gregset (gdb_gregset_t *gregsetp)
+supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
{
- ppc_linux_supply_gregset ((char *) gregsetp);
+ const struct regset *regset = ppc_linux_gregset (sizeof (long));
+
+ ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
}
void
-fill_gregset (gdb_gregset_t *gregsetp, int regno)
+fill_gregset (const struct regcache *regcache,
+ gdb_gregset_t *gregsetp, int regno)
{
- int regi;
- elf_greg_t *regp = (elf_greg_t *) gregsetp;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- for (regi = 0; regi < 32; regi++)
- {
- if ((regno == -1) || regno == regi)
- regcache_collect (regi, regp + PT_R0 + regi);
- }
+ const struct regset *regset = ppc_linux_gregset (sizeof (long));
- if ((regno == -1) || regno == PC_REGNUM)
- regcache_collect (PC_REGNUM, regp + PT_NIP);
- if ((regno == -1) || regno == tdep->ppc_lr_regnum)
- regcache_collect (tdep->ppc_lr_regnum, regp + PT_LNK);
- if ((regno == -1) || regno == tdep->ppc_cr_regnum)
- regcache_collect (tdep->ppc_cr_regnum, regp + PT_CCR);
- if ((regno == -1) || regno == tdep->ppc_xer_regnum)
- regcache_collect (tdep->ppc_xer_regnum, regp + PT_XER);
- if ((regno == -1) || regno == tdep->ppc_ctr_regnum)
- regcache_collect (tdep->ppc_ctr_regnum, regp + PT_CTR);
-#ifdef PT_MQ
- if (((regno == -1) || regno == tdep->ppc_mq_regnum)
- && (tdep->ppc_mq_regnum != -1))
- regcache_collect (tdep->ppc_mq_regnum, regp + PT_MQ);
-#endif
- if ((regno == -1) || regno == tdep->ppc_ps_regnum)
- regcache_collect (tdep->ppc_ps_regnum, regp + PT_MSR);
+ if (regno == -1)
+ memset (gregsetp, 0, sizeof (*gregsetp));
+ ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
}
void
-supply_fpregset (gdb_fpregset_t * fpregsetp)
+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
{
- ppc_linux_supply_fpregset ((char *) fpregsetp);
+ const struct regset *regset = ppc_linux_fpregset ();
+
+ ppc_supply_fpregset (regset, regcache, -1,
+ fpregsetp, sizeof (*fpregsetp));
}
-/* Given a pointer to a floating point register set in /proc format
- (fpregset_t *), update the register specified by REGNO from gdb's
- idea of the current floating point register set. If REGNO is -1,
- update them all. */
void
-fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
+fill_fpregset (const struct regcache *regcache,
+ gdb_fpregset_t *fpregsetp, int regno)
{
- int regi;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- for (regi = 0; regi < 32; regi++)
+ const struct regset *regset = ppc_linux_fpregset ();
+
+ ppc_collect_fpregset (regset, regcache, regno,
+ fpregsetp, sizeof (*fpregsetp));
+}
+
+static const struct target_desc *
+ppc_linux_read_description (struct target_ops *ops)
+{
+ int altivec = 0;
+
+ int tid = TIDGET (inferior_ptid);
+ if (tid == 0)
+ tid = PIDGET (inferior_ptid);
+
+ if (have_ptrace_getsetevrregs)
{
- if ((regno == -1) || (regno == FP0_REGNUM + regi))
- regcache_collect (FP0_REGNUM + regi, (char *) (*fpregsetp + regi));
+ struct gdb_evrregset_t evrregset;
+
+ if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
+ return tdesc_powerpc_e500l;
+
+ /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
+ Anything else needs to be reported. */
+ else if (errno != EIO)
+ perror_with_name (_("Unable to fetch SPE registers"));
}
- if ((regno == -1) || regno == tdep->ppc_fpscr_regnum)
- regcache_collect (tdep->ppc_fpscr_regnum, (char *) (*fpregsetp + regi));
+
+ if (have_ptrace_getvrregs)
+ {
+ gdb_vrregset_t vrregset;
+
+ if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
+ altivec = 1;
+
+ /* EIO means that the PTRACE_GETVRREGS request isn't supported.
+ Anything else needs to be reported. */
+ else if (errno != EIO)
+ perror_with_name (_("Unable to fetch AltiVec registers"));
+ }
+
+ /* Check for 64-bit inferior process. This is the case when the host is
+ 64-bit, and in addition the top bit of the MSR register is set. */
+#ifdef __powerpc64__
+ {
+ long msr;
+ errno = 0;
+ msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
+ if (errno == 0 && msr < 0)
+ return altivec? tdesc_powerpc_altivec64l : tdesc_powerpc_64l;
+ }
+#endif
+
+ return altivec? tdesc_powerpc_altivec32l : tdesc_powerpc_32l;
+}
+
+void _initialize_ppc_linux_nat (void);
+
+void
+_initialize_ppc_linux_nat (void)
+{
+ struct target_ops *t;
+
+ /* Fill in the generic GNU/Linux methods. */
+ t = linux_target ();
+
+ /* Add our register access methods. */
+ t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
+ t->to_store_registers = ppc_linux_store_inferior_registers;
+
+ /* Add our watchpoint methods. */
+ t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources;
+ t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
+ t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
+ t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
+ t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
+ t->to_stopped_data_address = ppc_linux_stopped_data_address;
+ t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
+
+ t->to_read_description = ppc_linux_read_description;
+
+ /* Register the target. */
+ linux_nat_add_target (t);
+ linux_nat_set_new_thread (t, ppc_linux_new_thread);
}
projects / deliverable / binutils-gdb.git / blobdiff