int wordsize; /* size in bytes of fixed-point word */
const struct reg *regs; /* from current variant */
int ppc_gp0_regnum; /* GPR register 0 */
- int ppc_gprs_pseudo_p; /* non-zero if GPRs are pseudo-registers */
int ppc_toc_regnum; /* TOC register */
int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
int ppc_cr_regnum; /* Condition register */
int ppc_mq_regnum; /* Multiply/Divide extension register */
int ppc_vr0_regnum; /* First AltiVec register */
int ppc_vrsave_regnum; /* Last AltiVec register */
+ int ppc_ev0_upper_regnum; /* First GPR upper half register */
int ppc_ev0_regnum; /* First ev register */
int ppc_ev31_regnum; /* Last ev register */
int ppc_acc_regnum; /* SPE 'acc' register */
int ppc_spefscr_regnum; /* SPE 'spefscr' register */
int lr_frame_offset; /* Offset to ABI specific location where
link register is saved. */
+
+ /* An array of integers, such that sim_regno[I] is the simulator
+ register number for GDB register number I, or -1 if the
+ simulator does not implement that register. */
+ int *sim_regno;
};
ppc_spr_sprg1 = 273,
ppc_spr_sprg2 = 274,
ppc_spr_sprg3 = 275,
+ ppc_spr_asr = 280,
ppc_spr_ear = 282,
ppc_spr_tbl = 284,
ppc_spr_tbu = 285,
ppc_spr_m_casid = 793,
ppc_spr_md_ap = 794,
ppc_spr_md_epn = 795,
- ppc_spr_md_twb = 796,
+ ppc_spr_m_twb = 796,
ppc_spr_md_twc = 797,
ppc_spr_md_rpn = 798,
ppc_spr_m_tw = 799,
+ ppc_spr_mi_dbcam = 816,
+ ppc_spr_mi_dbram0 = 817,
+ ppc_spr_mi_dbram1 = 818,
ppc_spr_md_dbcam = 824,
+ ppc_spr_md_cam = 824,
ppc_spr_md_dbram0 = 825,
+ ppc_spr_md_ram0 = 825,
ppc_spr_md_dbram1 = 826,
+ ppc_spr_md_ram1 = 826,
ppc_spr_ummcr0 = 936,
ppc_spr_upmc1 = 937,
ppc_spr_upmc2 = 938,