/* Target-dependent code for GDB, the GNU debugger.
- Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation,
- Inc.
+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007
+ Free Software Foundation, Inc.
This file is part of GDB.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
#ifndef PPC_TDEP_H
#define PPC_TDEP_H
CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
CORE_ADDR bpaddr);
-int ppc_linux_memory_remove_breakpoint (CORE_ADDR addr,
- gdb_byte *contents_cache);
+int ppc_linux_memory_remove_breakpoint (struct bp_target_info *bp_tgt);
struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
void ppc_linux_supply_gregset (struct regcache *regcache,
int regnum, const void *gregs, size_t size,
int ppc_ctr_regnum; /* Count register */
int ppc_xer_regnum; /* Integer exception register */
- /* On PPC and RS6000 variants that have no floating-point
- registers, the next two members will be -1. */
+ /* Not all PPC and RS6000 variants will have the registers
+ represented below. A -1 is used to indicate that the register
+ is not present in this variant. */
+
+ /* Floating-point registers. */
int ppc_fp0_regnum; /* floating-point register 0 */
- int ppc_fpscr_regnum; /* Floating point status and condition
- register */
+ int ppc_fpscr_regnum; /* fp status and condition register */
+
+ /* Segment registers. */
+ int ppc_sr0_regnum; /* segment register 0 */
- int ppc_sr0_regnum; /* segment register 0, or -1 on
- variants that have no segment
- registers. */
+ /* Multiplier-Quotient Register (older POWER architectures only). */
+ int ppc_mq_regnum;
- int ppc_mq_regnum; /* Multiply/Divide extension register */
+ /* Altivec registers. */
int ppc_vr0_regnum; /* First AltiVec register */
int ppc_vrsave_regnum; /* Last AltiVec register */
+
+ /* SPE registers. */
int ppc_ev0_upper_regnum; /* First GPR upper half register */
int ppc_ev0_regnum; /* First ev register */
int ppc_ev31_regnum; /* Last ev register */
int ppc_acc_regnum; /* SPE 'acc' register */
int ppc_spefscr_regnum; /* SPE 'spefscr' register */
- int lr_frame_offset; /* Offset to ABI specific location where
- link register is saved. */
+
+ /* Offset to ABI specific location where link register is saved. */
+ int lr_frame_offset;
/* An array of integers, such that sim_regno[I] is the simulator
register number for GDB register number I, or -1 if the
simulator does not implement that register. */
int *sim_regno;
+
+ /* Minimum possible text address. */
+ CORE_ADDR text_segment_base;
+
+ /* ISA-specific types. */
+ struct type *ppc_builtin_type_vec64;
+ struct type *ppc_builtin_type_vec128;
};
ppc_spr_pbu2 = 1023
};
-#endif
+/* Instruction size. */
+#define PPC_INSN_SIZE 4
+
+/* Estimate for the maximum number of instrctions in a function epilogue. */
+#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
+
+#endif /* ppc-tdep.h */