Workaround for Itanium A/B step errata

[deliverable/binutils-gdb.git] / gdb / regcache.c

diff --git a/gdb/regcache.c b/gdb/regcache.c
index c7bf6dcc091d35b670266000e3654c8121b575f7..2326b3485b9c52d58651edc1f351d721bab74921 100644 (file)
--- a/gdb/regcache.c
+++ b/gdb/regcache.c
@@ -24,6 +24,7 @@
 #include "inferior.h"
 #include "target.h"
 #include "gdbarch.h"
+#include "gdbcmd.h"
 
 /*
  * DATA STRUCTURE
@@ -716,7 +717,7 @@ supply_register (int regno, char *val)
    Ditto for write_pc.
 
    1999-06-08: The following were re-written so that it assumes the
-   existance of a TARGET_READ_PC et.al. macro.  A default generic
+   existence of a TARGET_READ_PC et.al. macro.  A default generic
    version of that macro is made available where needed.
 
    Since the ``TARGET_READ_PC'' et.al. macro is going to be controlled
@@ -867,6 +868,17 @@ write_fp (CORE_ADDR val)
   TARGET_WRITE_FP (val);
 }
 
+/* ARGSUSED */
+static void
+reg_flush_command (char *command, int from_tty)
+{
+  /* Force-flush the register cache.  */
+  registers_changed ();
+  if (from_tty)
+    printf_filtered ("Register cache flushed.\n");
+}
+
+
 static void
 build_regcache (void)
 {
@@ -889,4 +901,7 @@ _initialize_regcache (void)
   register_gdbarch_swap (&registers, sizeof (registers), NULL);
   register_gdbarch_swap (&register_valid, sizeof (register_valid), NULL);
   register_gdbarch_swap (NULL, 0, build_regcache);
+
+  add_com ("flushregs", class_maintenance, reg_flush_command,
+          "Force gdb to flush its register cache (maintainer command)");
 }