{ 0 }
};
+/* Define the FP register mapping. The kernel puts the 32 FP regs first, and
+ then FCSR. */
+
+static const struct regcache_map_entry riscv_linux_fregmap[] =
+{
+ { 32, RISCV_FIRST_FP_REGNUM, 0 },
+ { 1, RISCV_CSR_FCSR_REGNUM, 0 },
+ { 0 }
+};
+
/* Define the general register regset. */
static const struct regset riscv_linux_gregset =
riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset
};
+/* Define the FP register regset. */
+
+static const struct regset riscv_linux_fregset =
+{
+ riscv_linux_fregmap, regcache_supply_regset, regcache_collect_regset
+};
+
/* Define hook for core file support. */
static void
{
cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)),
&riscv_linux_gregset, NULL, cb_data);
-
- /* TODO: Add FP register support. */
+ /* The kernel is adding 8 bytes for FCSR. */
+ cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8,
+ (32 * riscv_isa_flen (gdbarch)) + 8,
+ &riscv_linux_fregset, NULL, cb_data);
}
/* Signal trampoline support. */