non_ir_ref_dynamic

[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c

diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 72ee05de2f37131e8181c74417eee08c51c2f6d0..4072464558ea436cfa6ca8cd784b64c41becc8ed 100644 (file)
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -106,6 +106,9 @@
     && (regnum) >= (tdep)->ppc_efpr0_regnum \
     && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
 
+/* Holds the current set of options to be passed to the disassembler.  */
+static char *powerpc_disassembler_options;
+
 /* The list of available "set powerpc ..." and "show powerpc ..."
    commands.  */
 static struct cmd_list_element *setpowerpccmdlist = NULL;
@@ -1162,7 +1165,7 @@ ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
    Load And Reserve instruction and ending with a Store Conditional
    instruction.  If such a sequence is found, attempt to step through it.
    A breakpoint is placed at the end of the sequence.  */
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
 ppc_deal_with_atomic_sequence (struct regcache *regcache)
 {
   struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -1177,11 +1180,10 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
   int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed).  */  
   const int atomic_sequence_length = 16; /* Instruction sequence length.  */
   int bc_insn_count = 0; /* Conditional branch instruction count.  */
-  VEC (CORE_ADDR) *next_pcs = NULL;
 
   /* Assume all atomic sequences start with a Load And Reserve instruction.  */
   if (!IS_LOAD_AND_RESERVE_INSN (insn))
-    return NULL;
+    return {};
 
   /* Assume that no atomic sequence is longer than "atomic_sequence_length" 
      instructions.  */
@@ -1199,8 +1201,8 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
           int absolute = insn & 2;
 
           if (bc_insn_count >= 1)
-            return 0; /* More than one conditional branch found, fallback 
-                         to the standard single-step code.  */
+            return {}; /* More than one conditional branch found, fallback
+                          to the standard single-step code.  */
  
          if (absolute)
            breaks[1] = immediate;
@@ -1218,7 +1220,7 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
   /* Assume that the atomic sequence ends with a Store Conditional
      instruction.  */
   if (!IS_STORE_CONDITIONAL_INSN (insn))
-    return NULL;
+    return {};
 
   closing_insn = loc;
   loc += PPC_INSN_SIZE;
@@ -1234,8 +1236,10 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
          || (breaks[1] >= pc && breaks[1] <= closing_insn)))
     last_breakpoint = 0;
 
+  std::vector<CORE_ADDR> next_pcs;
+
   for (index = 0; index <= last_breakpoint; index++)
-    VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+    next_pcs.push_back (breaks[index]);
 
   return next_pcs;
 }
@@ -3143,10 +3147,10 @@ rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
 struct variant
   {
     /* Name of this variant.  */
-    char *name;
+    const char *name;
 
     /* English description of the variant.  */
-    char *description;
+    const char *description;
 
     /* bfd_arch_info.arch corresponding to variant.  */
     enum bfd_architecture arch;
@@ -6609,6 +6613,10 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   else
     register_ppc_ravenscar_ops (gdbarch);
 
+  set_gdbarch_disassembler_options (gdbarch, &powerpc_disassembler_options);
+  set_gdbarch_valid_disassembler_options (gdbarch,
+                                         disassembler_options_powerpc ());
+
   return gdbarch;
 }