&& tdep->ppc_fpscr_regnum >= 0);
}
-/* Return non-zero if the architecture described by GDBARCH has
- VSX registers (vsr0 --- vsr63). */
-static int
-ppc_vsx_support_p (struct gdbarch *gdbarch)
-{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-
- return tdep->ppc_vsr0_regnum >= 0;
-}
-
/* Return non-zero if the architecture described by GDBARCH has
Altivec registers (vr0 --- vr31, vrsave and vscr). */
int
&& gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
offset += regsize - gdb_regsize;
}
- regcache_raw_supply (regcache, regnum, regs + offset);
+ regcache->raw_supply (regnum, regs + offset);
}
}
regsize - gdb_regsize);
}
}
- regcache_raw_collect (regcache, regnum, regs + offset);
+ regcache->raw_collect (regnum, regs + offset);
}
}
regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
}
-/* Supply register REGNUM in the VSX register set REGSET
- from the buffer specified by VSXREGS and LEN to register cache
- REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
-
-void
-ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
- int regnum, const void *vsxregs, size_t len)
-{
- struct gdbarch *gdbarch = regcache->arch ();
- struct gdbarch_tdep *tdep;
-
- if (!ppc_vsx_support_p (gdbarch))
- return;
-
- tdep = gdbarch_tdep (gdbarch);
-
- if (regnum == -1)
- {
- int i;
-
- for (i = tdep->ppc_vsr0_upper_regnum;
- i < tdep->ppc_vsr0_upper_regnum + 32;
- i++)
- ppc_supply_reg (regcache, i, (const gdb_byte *) vsxregs, 0, 8);
-
- return;
- }
- else
- ppc_supply_reg (regcache, regnum, (const gdb_byte *) vsxregs, 0, 8);
-}
-
/* Collect register REGNUM in the general-purpose register set
REGSET from register cache REGCACHE into the buffer specified by
GREGS and LEN. If REGNUM is -1, do this for all registers in
regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
}
-/* Collect register REGNUM in the VSX register set
- REGSET from register cache REGCACHE into the buffer specified by
- VSXREGS and LEN. If REGNUM is -1, do this for all registers in
- REGSET. */
-
-void
-ppc_collect_vsxregset (const struct regset *regset,
- const struct regcache *regcache,
- int regnum, void *vsxregs, size_t len)
-{
- struct gdbarch *gdbarch = regcache->arch ();
- struct gdbarch_tdep *tdep;
-
- if (!ppc_vsx_support_p (gdbarch))
- return;
-
- tdep = gdbarch_tdep (gdbarch);
-
- if (regnum == -1)
- {
- int i;
-
- for (i = tdep->ppc_vsr0_upper_regnum;
- i < tdep->ppc_vsr0_upper_regnum + 32;
- i++)
- ppc_collect_reg (regcache, i, (gdb_byte *) vsxregs, 0, 8);
-
- return;
- }
- else
- ppc_collect_reg (regcache, regnum, (gdb_byte *) vsxregs, 0, 8);
-}
-
static int
insn_changes_sp_or_jumps (unsigned long insn)
{
static enum register_status
do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer)
{
- regcache_raw_write (regcache, regnum, (const gdb_byte *) buffer);
+ regcache->raw_write (regnum, (const gdb_byte *) buffer);
return REG_VALID;
}
{
/* Write each half of the dl register into a separate
FP register. */
- regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
+ regcache->raw_write (tdep->ppc_fp0_regnum +
2 * reg_index, buffer);
- regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
+ regcache->raw_write (tdep->ppc_fp0_regnum +
2 * reg_index + 1, buffer + 8);
}
else
{
- regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
+ regcache->raw_write (tdep->ppc_fp0_regnum +
2 * reg_index + 1, buffer);
- regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
+ regcache->raw_write (tdep->ppc_fp0_regnum +
2 * reg_index, buffer + 8);
}
}
/* Write the portion that overlaps the VMX registers. */
if (reg_index > 31)
- regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
+ regcache->raw_write (tdep->ppc_vr0_regnum +
reg_index - 32, buffer);
else
/* Write the portion that overlaps the FPR registers. */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
- regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
+ regcache->raw_write (tdep->ppc_fp0_regnum +
reg_index, buffer);
- regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
+ regcache->raw_write (tdep->ppc_vsr0_upper_regnum +
reg_index, buffer + 8);
}
else
{
- regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
+ regcache->raw_write (tdep->ppc_fp0_regnum +
reg_index, buffer + 8);
- regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
+ regcache->raw_write (tdep->ppc_vsr0_upper_regnum +
reg_index, buffer);
}
}
int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
/* Write the portion that overlaps the VMX register. */
- regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index,
- offset, register_size (gdbarch, reg_nr),
- buffer);
+ regcache->raw_write_part (tdep->ppc_vr0_regnum + reg_index, offset,
+ register_size (gdbarch, reg_nr), buffer);
}
static enum register_status
return 0;
case 1014: /* Data Cache Block set to Zero */
- if (target_auxv_search (target_stack, AT_DCACHEBSIZE, &at_dcsz) <= 0
+ if (target_auxv_search (current_top_target (), AT_DCACHEBSIZE, &at_dcsz) <= 0
|| at_dcsz == 0)
at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */
have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
"mq");
- tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
+ tdesc_wordsize = tdesc_register_bitsize (feature, "pc") / 8;
if (wordsize == -1)
wordsize = tdesc_wordsize;
return NULL;
}
have_fpu = 1;
+
+ /* The fpscr register was expanded in isa 2.05 to 64 bits
+ along with the addition of the decimal floating point
+ facility. */
+ if (tdesc_register_bitsize (feature, "fpscr") > 32)
+ have_dfp = 1;
}
else
have_fpu = 0;
- /* The DFP pseudo-registers will be available when there are floating
- point registers. */
- have_dfp = have_fpu;
-
feature = tdesc_find_feature (tdesc,
"org.gnu.gdb.power.altivec");
if (feature != NULL)
projects / deliverable / binutils-gdb.git / blobdiff