/* Target-dependent code for GDB, the GNU debugger.
- Copyright (C) 1986-2017 Free Software Foundation, Inc.
+ Copyright (C) 1986-2018 Free Software Foundation, Inc.
This file is part of GDB.
#include "arch-utils.h"
#include "regcache.h"
#include "regset.h"
-#include "doublest.h"
+#include "target-float.h"
#include "value.h"
#include "parser-defs.h"
#include "osabi.h"
{
if (regsize > 4)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
int gdb_regsize = register_size (gdbarch, regnum);
if (gdb_regsize < regsize
&& gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
if (regsize > 4)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
int gdb_regsize = register_size (gdbarch, regnum);
if (gdb_regsize < regsize)
{
ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *gregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const struct ppc_reg_offsets *offsets
= (const struct ppc_reg_offsets *) regset->regmap;
ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *fpregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *vsxregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep;
if (!ppc_vsx_support_p (gdbarch))
ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *vrregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
const struct regcache *regcache,
int regnum, void *gregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const struct ppc_reg_offsets *offsets
= (const struct ppc_reg_offsets *) regset->regmap;
const struct regcache *regcache,
int regnum, void *fpregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
const struct regcache *regcache,
int regnum, void *vsxregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep;
if (!ppc_vsx_support_p (gdbarch))
const struct regcache *regcache,
int regnum, void *vrregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
|| (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
|| (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
-/* We can't displaced step atomic sequences. Otherwise this is just
- like simple_displaced_step_copy_insn. */
+typedef buf_displaced_step_closure ppc_displaced_step_closure;
+
+/* We can't displaced step atomic sequences. */
static struct displaced_step_closure *
ppc_displaced_step_copy_insn (struct gdbarch *gdbarch,
struct regcache *regs)
{
size_t len = gdbarch_max_insn_length (gdbarch);
- gdb_byte *buf = (gdb_byte *) xmalloc (len);
- struct cleanup *old_chain = make_cleanup (xfree, buf);
+ std::unique_ptr<ppc_displaced_step_closure> closure
+ (new ppc_displaced_step_closure (len));
+ gdb_byte *buf = closure->buf.data ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int insn;
"atomic sequence at %s\n",
paddress (gdbarch, from));
}
- do_cleanups (old_chain);
+
return NULL;
}
displaced_step_dump_bytes (gdb_stdlog, buf, len);
}
- discard_cleanups (old_chain);
- return (struct displaced_step_closure *) buf;
+ return closure.release ();
}
/* Fix up the state of registers and memory after having single-stepped
a displaced instruction. */
static void
ppc_displaced_step_fixup (struct gdbarch *gdbarch,
- struct displaced_step_closure *closure,
+ struct displaced_step_closure *closure_,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* Our closure is a copy of the instruction. */
- ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
- PPC_INSN_SIZE, byte_order);
+ ppc_displaced_step_closure *closure = (ppc_displaced_step_closure *) closure_;
+ ULONGEST insn = extract_unsigned_integer (closure->buf.data (),
+ PPC_INSN_SIZE, byte_order);
ULONGEST opcode = 0;
/* Offset for non PC-relative instructions. */
LONGEST offset = PPC_INSN_SIZE;
Load And Reserve instruction and ending with a Store Conditional
instruction. If such a sequence is found, attempt to step through it.
A breakpoint is placed at the end of the sequence. */
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
ppc_deal_with_atomic_sequence (struct regcache *regcache)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR pc = regcache_read_pc (regcache);
CORE_ADDR breaks[2] = {-1, -1};
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int bc_insn_count = 0; /* Conditional branch instruction count. */
- VEC (CORE_ADDR) *next_pcs = NULL;
/* Assume all atomic sequences start with a Load And Reserve instruction. */
if (!IS_LOAD_AND_RESERVE_INSN (insn))
- return NULL;
+ return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
instructions. */
int absolute = insn & 2;
if (bc_insn_count >= 1)
- return 0; /* More than one conditional branch found, fallback
- to the standard single-step code. */
+ return {}; /* More than one conditional branch found, fallback
+ to the standard single-step code. */
if (absolute)
breaks[1] = immediate;
/* Assume that the atomic sequence ends with a Store Conditional
instruction. */
if (!IS_STORE_CONDITIONAL_INSN (insn))
- return NULL;
+ return {};
closing_insn = loc;
loc += PPC_INSN_SIZE;
- insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
/* Insert a breakpoint right after the end of the atomic sequence. */
breaks[0] = loc;
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
remember just the first one, but skip over additional
ones. */
if (lr_reg == -1)
- lr_reg = (op & 0x03e00000) >> 21;
+ lr_reg = (op & 0x03e00000);
if (lr_reg == 0)
r0_contains_arg = 0;
continue;
offset = fdata->offset;
continue;
}
- else if ((op & 0xfc1f016a) == 0x7c01016e)
+ else if ((op & 0xfc1f016e) == 0x7c01016e)
{ /* stwux rX,r1,rY */
/* No way to figure out what r1 is going to be. */
fdata->frameless = 0;
#endif /* 0 */
if (pc == lim_pc && lr_reg >= 0)
- fdata->lr_register = lr_reg;
+ fdata->lr_register = lr_reg >> 21;
fdata->offset = -fdata->offset;
return last_prologue_pc;
int *optimizedp, int *unavailablep)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
- gdb_byte from[MAX_REGISTER_SIZE];
+ gdb_byte from[PPC_MAX_REGISTER_SIZE];
gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
from, optimizedp, unavailablep))
return 0;
- convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
- to, type);
+ target_float_convert (from, builtin_type (gdbarch)->builtin_double,
+ to, type);
*optimizedp = *unavailablep = 0;
return 1;
}
const gdb_byte *from)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
- gdb_byte to[MAX_REGISTER_SIZE];
+ gdb_byte to[PPC_MAX_REGISTER_SIZE];
gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
- convert_typed_floating (from, type,
- to, builtin_type (gdbarch)->builtin_double);
+ target_float_convert (from, type,
+ to, builtin_type (gdbarch)->builtin_double);
put_frame_register (frame, regnum, to);
}
e500_move_ev_register (move_ev_register_func move,
struct regcache *regcache, int ev_reg, void *buffer)
{
- struct gdbarch *arch = get_regcache_arch (regcache);
+ struct gdbarch *arch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
int reg_index;
gdb_byte *byte_buffer = (gdb_byte *) buffer;
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
/* Read two FP registers to form a whole dl register. */
- status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
- 2 * reg_index, buffer);
+ status = regcache->raw_read (tdep->ppc_fp0_regnum +
+ 2 * reg_index, buffer);
if (status == REG_VALID)
- status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
- 2 * reg_index + 1, buffer + 8);
+ status = regcache->raw_read (tdep->ppc_fp0_regnum +
+ 2 * reg_index + 1, buffer + 8);
}
else
{
- status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
- 2 * reg_index + 1, buffer);
+ status = regcache->raw_read (tdep->ppc_fp0_regnum +
+ 2 * reg_index + 1, buffer);
if (status == REG_VALID)
- status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
- 2 * reg_index, buffer + 8);
+ status = regcache->raw_read (tdep->ppc_fp0_regnum +
+ 2 * reg_index, buffer + 8);
}
return status;
/* Read the portion that overlaps the VMX registers. */
if (reg_index > 31)
- status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
- reg_index - 32, buffer);
+ status = regcache->raw_read (tdep->ppc_vr0_regnum +
+ reg_index - 32, buffer);
else
/* Read the portion that overlaps the FPR registers. */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
- status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
- reg_index, buffer);
+ status = regcache->raw_read (tdep->ppc_fp0_regnum +
+ reg_index, buffer);
if (status == REG_VALID)
- status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
- reg_index, buffer + 8);
+ status = regcache->raw_read (tdep->ppc_vsr0_upper_regnum +
+ reg_index, buffer + 8);
}
else
{
- status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
- reg_index, buffer + 8);
+ status = regcache->raw_read (tdep->ppc_fp0_regnum +
+ reg_index, buffer + 8);
if (status == REG_VALID)
- status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
- reg_index, buffer);
+ status = regcache->raw_read (tdep->ppc_vsr0_upper_regnum +
+ reg_index, buffer);
}
return status;
struct regcache *regcache,
int reg_nr, gdb_byte *buffer)
{
- struct gdbarch *regcache_arch = get_regcache_arch (regcache);
+ struct gdbarch *regcache_arch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
gdb_assert (regcache_arch == gdbarch);
struct regcache *regcache,
int reg_nr, const gdb_byte *buffer)
{
- struct gdbarch *regcache_arch = get_regcache_arch (regcache);
+ struct gdbarch *regcache_arch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
gdb_assert (regcache_arch == gdbarch);
return NULL;
}
-static int
-gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
-{
- if (info->endian == BFD_ENDIAN_BIG)
- return print_insn_big_powerpc (memaddr, info);
- else
- return print_insn_little_powerpc (memaddr, info);
-}
\f
static CORE_ADDR
rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
bfd abfd;
enum auto_boolean soft_float_flag = powerpc_soft_float_global;
int soft_float;
+ enum powerpc_long_double_abi long_double_abi = POWERPC_LONG_DOUBLE_AUTO;
enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
{
switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
- Tag_GNU_Power_ABI_FP))
+ Tag_GNU_Power_ABI_FP) & 3)
{
case 1:
soft_float_flag = AUTO_BOOLEAN_FALSE;
}
}
+ if (long_double_abi == POWERPC_LONG_DOUBLE_AUTO && from_elf_exec)
+ {
+ switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
+ Tag_GNU_Power_ABI_FP) >> 2)
+ {
+ case 1:
+ long_double_abi = POWERPC_LONG_DOUBLE_IBM128;
+ break;
+ case 3:
+ long_double_abi = POWERPC_LONG_DOUBLE_IEEE128;
+ break;
+ default:
+ break;
+ }
+ }
+
if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
{
switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
continue;
if (tdep && tdep->soft_float != soft_float)
continue;
+ if (tdep && tdep->long_double_abi != long_double_abi)
+ continue;
if (tdep && tdep->vector_abi != vector_abi)
continue;
if (tdep && tdep->wordsize == wordsize)
tdep->wordsize = wordsize;
tdep->elf_abi = elf_abi;
tdep->soft_float = soft_float;
+ tdep->long_double_abi = long_double_abi;
tdep->vector_abi = vector_abi;
gdbarch = gdbarch_alloc (&info, tdep);
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
- /* Select instruction printer. */
- if (arch == bfd_arch_rs6000)
- set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
- else
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
-
set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
if (have_spe)
set_gdbarch_displaced_step_hw_singlestep (gdbarch,
ppc_displaced_step_hw_singlestep);
set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
- set_gdbarch_displaced_step_free_closure (gdbarch,
- simple_displaced_step_free_closure);
set_gdbarch_displaced_step_location (gdbarch,
displaced_step_at_entry_point);
/* Hook in ABI-specific overrides, if they have been registered. */
info.target_desc = tdesc;
- info.tdep_info = tdesc_data;
+ info.tdesc_data = tdesc_data;
gdbarch_init_osabi (info, gdbarch);
switch (info.osabi)
/* PowerPC-specific commands. */
static void
-set_powerpc_command (char *args, int from_tty)
+set_powerpc_command (const char *args, int from_tty)
{
printf_unfiltered (_("\
\"set powerpc\" must be followed by an appropriate subcommand.\n"));
}
static void
-show_powerpc_command (char *args, int from_tty)
+show_powerpc_command (const char *args, int from_tty)
{
cmd_show_list (showpowerpccmdlist, from_tty, "");
}
static void
-powerpc_set_soft_float (char *args, int from_tty,
+powerpc_set_soft_float (const char *args, int from_tty,
struct cmd_list_element *c)
{
struct gdbarch_info info;
}
static void
-powerpc_set_vector_abi (char *args, int from_tty,
+powerpc_set_vector_abi (const char *args, int from_tty,
struct cmd_list_element *c)
{
struct gdbarch_info info;
'struct ppc_insn_pattern' objects, terminated by an entry whose
mask is zero.
- When the match is successful, fill INSN[i] with what PATTERN[i]
+ When the match is successful, fill INSNS[i] with what PATTERN[i]
matched. If PATTERN[i] is optional, and the instruction wasn't
- present, set INSN[i] to 0 (which is not a valid PPC instruction).
- INSN should have as many elements as PATTERN. Note that, if
- PATTERN contains optional instructions which aren't present in
- memory, then INSN will have holes, so INSN[i] isn't necessarily the
- i'th instruction in memory. */
+ present, set INSNS[i] to 0 (which is not a valid PPC instruction).
+ INSNS should have as many elements as PATTERN, minus the terminator.
+ Note that, if PATTERN contains optional instructions which aren't
+ present in memory, then INSNS will have holes, so INSNS[i] isn't
+ necessarily the i'th instruction in memory. */
int
ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
- struct ppc_insn_pattern *pattern,
+ const struct ppc_insn_pattern *pattern,
unsigned int *insns)
{
int i;
/* Initialization code. */
-/* -Wmissing-prototypes */
-extern initialize_file_ftype _initialize_rs6000_tdep;
-
void
_initialize_rs6000_tdep (void)
{
projects / deliverable / binutils-gdb.git / blobdiff