{
#define INSNLEN(OPCODE) 4
- static char breakp[] = BREAKPOINT;
+ static char le_breakp[] = LITTLE_BREAKPOINT;
+ static char be_breakp[] = BIG_BREAKPOINT;
+ char *breakp = TARGET_BYTE_ORDER == BIG_ENDIAN ? be_breakp : le_breakp;
int ii, insn;
CORE_ADDR loc;
CORE_ADDR breaks[2];
If the next is not a nop, this branch was part of the function
prologue. */
- if (op == 0x4def7b82 || /* crorc 15, 15, 15 */
+ if (op == 0x4def7b82 || /* crorc 15, 15, 15 */
op == 0x0)
- return pc - 4; /* don't skip over this branch */
+ return pc - 4; /* don't skip over this branch */
}
- if ((op & 0xfc1f0000) == 0xd8010000) { /* stfd Rx,NUM(r1) */
- pc += 4; /* store floating register double */
+ if ((op & 0xfc1f0000) == 0xd8010000) { /* stfd Rx,NUM(r1) */
+ pc += 4; /* store floating register double */
op = read_memory_integer (pc, 4);
}
- if ((op & 0xfc1f0000) == 0xbc010000) { /* stm Rx, NUM(r1) */
+ if ((op & 0xfc1f0000) == 0xbc010000) { /* stm Rx, NUM(r1) */
pc += 4;
op = read_memory_integer (pc, 4);
}
- while (((tmp = op >> 16) == 0x9001) || /* st r0, NUM(r1) */
- (tmp == 0x9421) || /* stu r1, NUM(r1) */
- (tmp == 0x93e1)) /* st r31,NUM(r1) */
- {
+ while ((op & 0xfc1f0000) == 0x90010000 && /* st rx,NUM(r1), rx >= r13 */
+ (op & 0x03e00000) >= 0x01a00000) {
+ pc += 4;
+ op = read_memory_integer (pc, 4);
+ }
+
+ if (op == 0x90010008) { /* st r0,8(r1) */
+ pc += 4;
+ op = read_memory_integer (pc, 4);
+ }
+
+ if (op == 0x91810004) { /* st r12,4(r1) */
+ pc += 4;
+ op = read_memory_integer (pc, 4);
+ }
+
+ if ((op & 0xffff0000) == 0x94210000) { /* stu r1,NUM(r1) */
pc += 4;
op = read_memory_integer (pc, 4);
}
sp = read_register(SP_REGNUM);
pc = read_register(PC_REGNUM);
- store_address (pc, 4, pc_targ);
+ store_address (pc_targ, 4, pc);
dummy_frame_addr [dummy_frame_count++] = sp;
/* this is called from xcoffread.c */
void
-xcoff_add_toc_to_loadinfo (unsigned long tocoff)
+xcoff_add_toc_to_loadinfo (tocoff)
+ unsigned long tocoff;
{
while (loadinfotocindex >= loadinfolen) {
loadinfolen += LOADINFOLEN;
}
-/* FIXME: This assumes that the "textorg" and "dataorg" elements
+/* Note that this assumes that the "textorg" and "dataorg" elements
of a member of this array are correlated with the "toc_offset"
- element of the same member. But they are sequentially assigned in wildly
- different places, and probably there is no correlation. FIXME! */
+ element of the same member. This is taken care of because the loops
+ which assign the former (in xcoff_relocate_symtab or xcoff_relocate_core)
+ and the latter (in scan_xcoff_symtab, via vmap_symtab, in vmap_ldinfo
+ or xcoff_relocate_core) traverse the same objfiles in the same order. */
static CORE_ADDR
find_toc_address (pc)
return loadinfo[toc_entry].dataorg + loadinfo[toc_entry].toc_offset;
}
+#ifdef GDB_TARGET_POWERPC
+int
+gdb_print_insn_powerpc (memaddr, info)
+ bfd_vma memaddr;
+ disassemble_info *info;
+{
+ if (TARGET_BYTE_ORDER == BIG_ENDIAN)
+ return print_insn_big_powerpc (memaddr, info);
+ else
+ return print_insn_little_powerpc (memaddr, info);
+}
+#endif
+
void
_initialize_rs6000_tdep ()
{
/* FIXME, this should not be decided via ifdef. */
#ifdef GDB_TARGET_POWERPC
- tm_print_insn = print_insn_big_powerpc;
+ tm_print_insn = gdb_print_insn_powerpc;
#else
tm_print_insn = print_insn_rs6000;
#endif