* inftarg.c (child_thread_alive): New function to see if a

[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c

diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index f08c77d7b80919a0fd6ff9e25990d5565a485b02..89c3ddd54d2b4a59f6312a10a7a2ff82c7980ec9 100644 (file)
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -78,10 +78,14 @@ branch_dest (opcode, instr, pc, safety)
   switch (opcode) {
      case 18   :
        immediate = ((instr & ~3) << 6) >> 6;   /* br unconditional */
+       if (absolute)
+         dest = immediate;     
+       else
+         dest = pc + immediate;
+       break;
 
      case 16   :  
-       if (opcode != 18)                       /* br conditional */
-         immediate = ((instr & ~3) << 16) >> 16;
+        immediate = ((instr & ~3) << 16) >> 16;        /* br conditional */
        if (absolute)
          dest = immediate;     
        else
@@ -122,7 +126,9 @@ single_step (signal)
 {
 #define        INSNLEN(OPCODE)  4
 
-  static char breakp[] = BREAKPOINT;
+  static char le_breakp[] = LITTLE_BREAKPOINT;
+  static char be_breakp[] = BIG_BREAKPOINT;
+  char *breakp = TARGET_BYTE_ORDER == BIG_ENDIAN ? be_breakp : le_breakp;
   int ii, insn;
   CORE_ADDR loc;
   CORE_ADDR breaks[2];
@@ -131,7 +137,7 @@ single_step (signal)
   if (!one_stepped) {
     loc = read_pc ();
 
-    read_memory (loc, (char *) &insn, 4);
+    insn = read_memory_integer (loc, 4);
 
     breaks[0] = loc + INSNLEN(insn);
     opcode = insn >> 26;
@@ -205,25 +211,38 @@ CORE_ADDR pc;
        If the next is not a nop, this branch was part of the function
        prologue. */
 
-    if (op == 0x4def7b82 ||            /* crorc 15, 15, 15 */
+    if (op == 0x4def7b82 ||                    /* crorc 15, 15, 15 */
        op == 0x0)
-      return pc - 4;                   /* don't skip over this branch */
+      return pc - 4;                           /* don't skip over this branch */
   }
 
-  if ((op & 0xfc1f0000) == 0xd8010000) { /* stfd Rx,NUM(r1) */
-    pc += 4;                            /* store floating register double */
+  if ((op & 0xfc1f0000) == 0xd8010000) {       /* stfd Rx,NUM(r1) */
+    pc += 4;                                   /* store floating register double */
     op = read_memory_integer (pc, 4);
   }
 
-  if ((op & 0xfc1f0000) == 0xbc010000) { /* stm Rx, NUM(r1) */
+  if ((op & 0xfc1f0000) == 0xbc010000) {       /* stm Rx, NUM(r1) */
     pc += 4;
     op = read_memory_integer (pc, 4);
   }
 
-  while (((tmp = op >> 16) == 0x9001) || /* st   r0, NUM(r1) */
-        (tmp == 0x9421) ||             /* stu  r1, NUM(r1) */
-        (tmp == 0x93e1))               /* st   r31,NUM(r1) */
-  {
+  while ((op & 0xfc1f0000) == 0x90010000 &&    /* st rx,NUM(r1), rx >= r13 */
+        (op & 0x03e00000) >= 0x01a00000) {
+    pc += 4;
+    op = read_memory_integer (pc, 4);
+  }
+
+  if (op == 0x90010008) {                      /* st r0,8(r1) */
+    pc += 4;
+    op = read_memory_integer (pc, 4);
+  }
+
+  if (op == 0x91810004) {                      /* st r12,4(r1) */
+    pc += 4;
+    op = read_memory_integer (pc, 4);
+  }
+        
+  if ((op & 0xffff0000) == 0x94210000) {       /* stu r1,NUM(r1) */
     pc += 4;
     op = read_memory_integer (pc, 4);
   }
@@ -322,6 +341,8 @@ push_dummy_frame ()
 {
   /* stack pointer.  */
   CORE_ADDR sp;
+  /* Same thing, target byte order.  */
+  char sp_targ[4];
 
   /* link register.  */
   CORE_ADDR pc;
@@ -344,7 +365,7 @@ push_dummy_frame ()
   
   sp = read_register(SP_REGNUM);
   pc = read_register(PC_REGNUM);
-  memcpy (pc_targ, (char *) &pc, 4);
+  store_address (pc_targ, 4, pc);
 
   dummy_frame_addr [dummy_frame_count++] = sp;
 
@@ -383,7 +404,8 @@ push_dummy_frame ()
   }
 
   /* Save sp or so called back chain right here. */
-  write_memory (sp-DUMMY_FRAME_SIZE, (char *)&sp, 4);
+  store_address (sp_targ, 4, sp);
+  write_memory (sp-DUMMY_FRAME_SIZE, sp_targ, 4);
   sp -= DUMMY_FRAME_SIZE;
 
   /* And finally, this is the back chain. */
@@ -852,7 +874,9 @@ ran_out_of_registers_for_arguments:
   read_memory (saved_sp, tmp_buffer, 24);
   write_memory (sp, tmp_buffer, 24);
 
-    write_memory (sp, (char *)&saved_sp, 4);   /* set back chain properly */
+  /* set back chain properly */
+  store_address (tmp_buffer, 4, saved_sp);
+  write_memory (sp, tmp_buffer, 4);
 
   target_store_registers (-1);
   return sp;
@@ -1150,7 +1174,8 @@ free_loadinfo ()
 /* this is called from xcoffread.c */
 
 void
-xcoff_add_toc_to_loadinfo (unsigned long tocoff)
+xcoff_add_toc_to_loadinfo (tocoff)
+     unsigned long tocoff;
 {
   while (loadinfotocindex >= loadinfolen) {
     loadinfolen += LOADINFOLEN;
@@ -1176,10 +1201,12 @@ add_text_to_loadinfo (textaddr, dataaddr)
 }
 
 
-/* FIXME:  This assumes that the "textorg" and "dataorg" elements
+/* Note that this assumes that the "textorg" and "dataorg" elements
    of a member of this array are correlated with the "toc_offset"
-   element of the same member.  But they are sequentially assigned in wildly
-   different places, and probably there is no correlation.  FIXME!  */
+   element of the same member.  This is taken care of because the loops
+   which assign the former (in xcoff_relocate_symtab or xcoff_relocate_core)
+   and the latter (in scan_xcoff_symtab, via vmap_symtab, in vmap_ldinfo
+   or xcoff_relocate_core) traverse the same objfiles in the same order.  */
 
 static CORE_ADDR
 find_toc_address (pc)
@@ -1196,12 +1223,25 @@ find_toc_address (pc)
   return loadinfo[toc_entry].dataorg + loadinfo[toc_entry].toc_offset;
 }
 
+#ifdef GDB_TARGET_POWERPC
+int
+gdb_print_insn_powerpc (memaddr, info)
+     bfd_vma memaddr;
+     disassemble_info *info;
+{
+  if (TARGET_BYTE_ORDER == BIG_ENDIAN)
+    return print_insn_big_powerpc (memaddr, info);
+  else
+    return print_insn_little_powerpc (memaddr, info);
+}
+#endif
+
 void
 _initialize_rs6000_tdep ()
 {
   /* FIXME, this should not be decided via ifdef. */
 #ifdef GDB_TARGET_POWERPC
-  tm_print_insn = print_insn_big_powerpc;
+  tm_print_insn = gdb_print_insn_powerpc;
 #else
   tm_print_insn = print_insn_rs6000;
 #endif