case 397: /* Store VSX Vector with Length */
case 429: /* Store VSX Vector Left-justified with Length */
+ ra = 0;
if (PPC_RA (insn) != 0)
regcache_raw_read_unsigned (regcache,
- tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
+ tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
+ ea = ra;
regcache_raw_read_unsigned (regcache,
tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
/* Store up to 16 bytes. */
case 710: /* Store Word Atomic */
case 742: /* Store Doubleword Atomic */
+ ra = 0;
if (PPC_RA (insn) != 0)
regcache_raw_read_unsigned (regcache,
- tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
+ tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
+ ea = ra;
switch (ext)
{
case 710: /* Store Word Atomic */
tdep->ppc_fp0_regnum + PPC_FRT (insn));
if (PPC_RC (insn))
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ return 0;
}
switch (ext & 0xff)
if (PPC_RC (insn))
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
- break;
+ return 0;
case 354: /* DFP Extract Biased Exponent Quad */
record_full_arch_list_add_reg (regcache,
if (PPC_RC (insn))
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
- break;
+ return 0;
case 0: /* Floating Compare Unordered */
case 32: /* Floating Compare Ordered */