-/* Target-dependent code for Hitachi Super-H, for GDB.
+/* Target-dependent code for Renesas Super-H, for GDB.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
static const char *
sh_generic_register_name (int reg_nr)
{
- static char *register_names[] =
- {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ static char *register_names[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"fpul", "fpscr",
- "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
- "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
- "ssr", "spc",
+ "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
+ "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
+ "ssr", "spc",
"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
};
static const char *
sh_sh_register_name (int reg_nr)
{
- static char *register_names[] =
- {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
- "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
+ static char *register_names[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
static const char *
sh_sh3_register_name (int reg_nr)
{
- static char *register_names[] =
- {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
- "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "ssr", "spc",
+ static char *register_names[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "ssr", "spc",
"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
};
static const char *
sh_sh3e_register_name (int reg_nr)
{
- static char *register_names[] =
- {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ static char *register_names[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"fpul", "fpscr",
- "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
- "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
- "ssr", "spc",
+ "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
+ "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
+ "ssr", "spc",
"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
};
static const char *
sh_sh2e_register_name (int reg_nr)
{
- static char *register_names[] =
- {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ static char *register_names[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"fpul", "fpscr",
- "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
- "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
- "", "",
+ "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
+ "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
+ "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
};
static const char *
sh_sh_dsp_register_name (int reg_nr)
{
- static char *register_names[] =
- {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
- "", "dsr",
- "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
- "y0", "y1", "", "", "", "", "", "mod",
- "", "",
- "rs", "re", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
+ static char *register_names[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ "", "dsr",
+ "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
+ "y0", "y1", "", "", "", "", "", "mod",
+ "", "",
+ "rs", "re", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
static const char *
sh_sh3_dsp_register_name (int reg_nr)
{
- static char *register_names[] =
- {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
- "", "dsr",
- "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
- "y0", "y1", "", "", "", "", "", "mod",
- "ssr", "spc",
- "rs", "re", "", "", "", "", "", "",
- "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
- "", "", "", "", "", "", "", "",
+ static char *register_names[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ "", "dsr",
+ "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
+ "y0", "y1", "", "", "", "", "", "mod",
+ "ssr", "spc",
+ "rs", "re", "", "", "", "", "", "",
+ "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
+ "", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
static const char *
sh_sh4_register_name (int reg_nr)
{
- static char *register_names[] =
- {
+ static char *register_names[] = {
/* general registers 0-15 */
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
/* 16 - 22 */
- "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
/* 23, 24 */
"fpul", "fpscr",
/* floating point registers 25 - 40 */
- "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
- "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
+ "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
+ "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
/* 41, 42 */
- "ssr", "spc",
+ "ssr", "spc",
/* bank 0 43 - 50 */
"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
/* bank 1 51 - 58 */
"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
/* double precision (pseudo) 59 - 66 */
- "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
+ "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
/* vectors (pseudo) 67 - 70 */
- "fv0", "fv4", "fv8", "fv12",
+ "fv0", "fv4", "fv8", "fv12",
/* FIXME: missing XF 71 - 86 */
/* FIXME: missing XD 87 - 94 */
};
return register_names[reg_nr];
}
+static const char *
+sh_sh4_nofpu_register_name (int reg_nr)
+{
+ static char *register_names[] = {
+ /* general registers 0-15 */
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ /* 16 - 22 */
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ /* 23, 24 */
+ "", "",
+ /* floating point registers 25 - 40 -- not for nofpu target */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* 41, 42 */
+ "ssr", "spc",
+ /* bank 0 43 - 50 */
+ "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
+ /* bank 1 51 - 58 */
+ "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
+ /* double precision (pseudo) 59 - 66 -- not for nofpu target */
+ "", "", "", "", "", "", "", "",
+ /* vectors (pseudo) 67 - 70 -- not for nofpu target */
+ "", "", "", "",
+ };
+ if (reg_nr < 0)
+ return NULL;
+ if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
+ return NULL;
+ return register_names[reg_nr];
+}
+
+static const char *
+sh_sh4al_dsp_register_name (int reg_nr)
+{
+ static char *register_names[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
+ "", "dsr",
+ "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
+ "y0", "y1", "", "", "", "", "", "mod",
+ "ssr", "spc",
+ "rs", "re", "", "", "", "", "", "",
+ "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
+ "", "", "", "", "", "", "", "",
+ };
+ if (reg_nr < 0)
+ return NULL;
+ if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
+ return NULL;
+ return register_names[reg_nr];
+}
+
static const unsigned char *
sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
{
/* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
- static unsigned char breakpoint[] = {0xc3, 0xc3};
-
+ static unsigned char breakpoint[] = { 0xc3, 0xc3 };
+
*lenptr = sizeof (breakpoint);
return breakpoint;
}
-static CORE_ADDR
-sh_push_dummy_code (struct gdbarch *gdbarch,
- CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc,
- struct value **args, int nargs,
- struct type *value_type,
- CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
-{
- /* Allocate space sufficient for a breakpoint. */
- sp = (sp - 2) & ~1;
- /* Store the address of that breakpoint */
- *bp_addr = sp;
- /* sh always starts the call at the callee's entry point. */
- *real_pc = funaddr;
- return sp;
-}
-
/* Prologue looks like
mov.l r14,@-r15
sts.l pr,@-r15
/* Disassemble an instruction. */
static int
-gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
+gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
{
info->endian = TARGET_BYTE_ORDER;
return print_insn_sh (memaddr, info);
static CORE_ADDR
sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
struct sh_frame_cache *cache)
-{
+{
ULONGEST inst;
CORE_ADDR opc;
int offset;
cache->sp_offset -= offset;
}
else if (IS_MOVW_PCREL_TO_REG (inst))
- {
+ {
if (sav_reg < 0)
{
reg = GET_TARGET_REG (inst);
sav_reg = reg;
offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
sav_offset =
- read_memory_integer (((pc + 4) & ~3) + offset, 2);
+ read_memory_integer (((pc + 4) & ~3) + offset, 2);
}
}
}
else if (IS_MOVL_PCREL_TO_REG (inst))
- {
+ {
if (sav_reg < 0)
{
reg = (inst & 0x0f00) >> 8;
sav_reg = reg;
offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
sav_offset =
- read_memory_integer (((pc + 4) & ~3) + offset, 4);
+ read_memory_integer (((pc + 4) & ~3) + offset, 4);
}
}
}
else if (IS_SUB_REG_FROM_SP (inst))
- {
+ {
reg = GET_SOURCE_REG (inst);
if (sav_reg > 0 && reg == sav_reg)
{
}
}
else if (IS_MOV_SP_FP (inst))
- {
+ {
if (!cache->uses_fp)
cache->uses_fp = 1;
/* At this point, only allow argument register moves to other
{
inst = read_memory_integer (pc, 2);
if (IS_MOV_ARG_TO_IND_R14 (inst))
- {
+ {
reg = GET_SOURCE_REG (inst);
if (cache->sp_offset > 0)
- cache->saved_regs[reg] = cache->sp_offset;
+ cache->saved_regs[reg] = cache->sp_offset;
}
else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
- {
+ {
reg = GET_SOURCE_REG (inst);
offset = (inst & 0xf) * 4;
if (cache->sp_offset > offset)
cache->saved_regs[reg] = cache->sp_offset - offset;
}
else if (IS_MOV_ARG_TO_REG (inst))
- continue;
+ continue;
else
break;
}
break;
}
-#if 0 /* This used to just stop when it found an instruction that
- was not considered part of the prologue. Now, we just
- keep going looking for likely instructions. */
+#if 0 /* This used to just stop when it found an instruction that
+ was not considered part of the prologue. Now, we just
+ keep going looking for likely instructions. */
else
break;
#endif
return pc;
}
-/* Should call_function allocate stack space for a struct return? */
+/* The ABI says:
+
+ Aggregate types not bigger than 8 bytes that have the same size and
+ alignment as one of the integer scalar types are returned in the
+ same registers as the integer type they match.
+
+ For example, a 2-byte aligned structure with size 2 bytes has the
+ same size and alignment as a short int, and will be returned in R0.
+ A 4-byte aligned structure with size 8 bytes has the same size and
+ alignment as a long long int, and will be returned in R0 and R1.
+
+ When an aggregate type is returned in R0 and R1, R0 contains the
+ first four bytes of the aggregate, and R1 contains the
+ remainder. If the size of the aggregate type is not a multiple of 4
+ bytes, the aggregate is tail-padded up to a multiple of 4
+ bytes. The value of the padding is undefined. For little-endian
+ targets the padding will appear at the most significant end of the
+ last element, for big-endian targets the padding appears at the
+ least significant end of the last element.
+
+ All other aggregate types are returned by address. The caller
+ function passes the address of an area large enough to hold the
+ aggregate value in R2. The called function stores the result in
+ this location.
+
+ To reiterate, structs smaller than 8 bytes could also be returned
+ in memory, if they don't pass the "same size and alignment as an
+ integer type" rule.
+
+ For example, in
+
+ struct s { char c[3]; } wibble;
+ struct s foo(void) { return wibble; }
+
+ the return value from foo() will be in memory, not
+ in R0, because there is no 3-byte integer type.
+
+ Similarly, in
+
+ struct s { char c[2]; } wibble;
+ struct s foo(void) { return wibble; }
+
+ because a struct containing two chars has alignment 1, that matches
+ type char, but size 2, that matches type short. There's no integer
+ type that has alignment 1 and size 2, so the struct is returned in
+ memory.
+
+*/
+
static int
sh_use_struct_convention (int gcc_p, struct type *type)
{
int len = TYPE_LENGTH (type);
int nelem = TYPE_NFIELDS (type);
- return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
- (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
+
+ /* Non-power of 2 length types and types bigger than 8 bytes (which don't
+ fit in two registers anyway) use struct convention. */
+ if (len != 1 && len != 2 && len != 4 && len != 8)
+ return 1;
+
+ /* Scalar types and aggregate types with exactly one field are aligned
+ by definition. They are returned in registers. */
+ if (nelem <= 1)
+ return 0;
+
+ /* If the first field in the aggregate has the same length as the entire
+ aggregate type, the type is returned in registers. */
+ if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
+ return 0;
+
+ /* If the size of the aggregate is 8 bytes and the first field is
+ of size 4 bytes its alignment is equal to long long's alignment,
+ so it's returned in registers. */
+ if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
+ return 0;
+
+ /* Otherwise use struct convention. */
+ return 1;
}
/* Extract from an array REGBUF containing the (raw) register state
/* Function: push_dummy_call (formerly push_arguments)
Setup the function arguments for calling a function in the inferior.
- On the Hitachi SH architecture, there are four registers (R4 to R7)
+ On the Renesas SH architecture, there are four registers (R4 to R7)
which are dedicated for passing function arguments. Up to the first
four arguments (depending on size) may go into these registers.
The rest go on the stack.
not displace any of the other arguments passed in via registers R4
to R7. */
+/* Helper function to justify value in register according to endianess. */
+static char *
+sh_justify_value_in_reg (struct value *val, int len)
+{
+ static char valbuf[4];
+
+ memset (valbuf, 0, sizeof (valbuf));
+ if (len < 4)
+ {
+ /* value gets right-justified in the register or stack word */
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
+ else
+ memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
+ return valbuf;
+ }
+ return (char *) VALUE_CONTENTS (val);
+}
+
+/* Helper function to eval number of bytes to allocate on stack. */
static CORE_ADDR
-sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
+sh_stack_allocsize (int nargs, struct value **args)
+{
+ int stack_alloc = 0;
+ while (nargs-- > 0)
+ stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
+ return stack_alloc;
+}
+
+/* Helper functions for getting the float arguments right. Registers usage
+ depends on the ABI and the endianess. The comments should enlighten how
+ it's intended to work. */
+
+/* This array stores which of the float arg registers are already in use. */
+static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
+
+/* This function just resets the above array to "no reg used so far". */
+static void
+sh_init_flt_argreg (void)
+{
+ memset (flt_argreg_array, 0, sizeof flt_argreg_array);
+}
+
+/* This function returns the next register to use for float arg passing.
+ It returns either a valid value between FLOAT_ARG0_REGNUM and
+ FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
+ FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
+
+ Note that register number 0 in flt_argreg_array corresponds with the
+ real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
+ 29) the parity of the register number is preserved, which is important
+ for the double register passing test (see the "argreg & 1" test below). */
+static int
+sh_next_flt_argreg (int len)
+{
+ int argreg;
+
+ /* First search for the next free register. */
+ for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
+ ++argreg)
+ if (!flt_argreg_array[argreg])
+ break;
+
+ /* No register left? */
+ if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
+ return FLOAT_ARGLAST_REGNUM + 1;
+
+ if (len == 8)
+ {
+ /* Doubles are always starting in a even register number. */
+ if (argreg & 1)
+ {
+ flt_argreg_array[argreg] = 1;
+
+ ++argreg;
+
+ /* No register left? */
+ if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
+ return FLOAT_ARGLAST_REGNUM + 1;
+ }
+ /* Also mark the next register as used. */
+ flt_argreg_array[argreg + 1] = 1;
+ }
+ else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
+ {
+ /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
+ if (!flt_argreg_array[argreg + 1])
+ ++argreg;
+ }
+ flt_argreg_array[argreg] = 1;
+ return FLOAT_ARG0_REGNUM + argreg;
+}
+
+/* Helper function which figures out, if a type is treated like a float type.
+
+ The FPU ABIs have a special way how to treat types as float types.
+ Structures with exactly one member, which is of type float or double, are
+ treated exactly as the base types float or double:
+
+ struct sf {
+ float f;
+ };
+
+ struct sd {
+ double d;
+ };
+
+ are handled the same way as just
+
+ float f;
+
+ double d;
+
+ As a result, arguments of these struct types are pushed into floating point
+ registers exactly as floats or doubles, using the same decision algorithm.
+
+ The same is valid if these types are used as function return types. The
+ above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
+ or even using struct convention as it is for other structs. */
+
+static int
+sh_treat_as_flt_p (struct type *type)
+{
+ int len = TYPE_LENGTH (type);
+
+ /* Ordinary float types are obviously treated as float. */
+ if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ return 1;
+ /* Otherwise non-struct types are not treated as float. */
+ if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
+ return 0;
+ /* Otherwise structs with more than one memeber are not treated as float. */
+ if (TYPE_NFIELDS (type) != 1)
+ return 0;
+ /* Otherwise if the type of that member is float, the whole type is
+ treated as float. */
+ if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
+ return 1;
+ /* Otherwise it's not treated as float. */
+ return 0;
+}
+
+static CORE_ADDR
+sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
CORE_ADDR func_addr,
- struct regcache *regcache,
+ struct regcache *regcache,
CORE_ADDR bp_addr, int nargs,
- struct value **args,
+ struct value **args,
CORE_ADDR sp, int struct_return,
CORE_ADDR struct_addr)
{
- int stack_offset, stack_alloc;
- int argreg, flt_argreg;
+ int stack_offset = 0;
+ int argreg = ARG0_REGNUM;
+ int flt_argreg = 0;
int argnum;
struct type *type;
CORE_ADDR regval;
char *val;
- char valbuf[4];
- int len;
- int odd_sized_struct;
+ int len, reg_size = 0;
+ int pass_on_stack = 0;
+ int treat_as_flt;
/* first force sp to a 4-byte alignment */
sp = sh_frame_align (gdbarch, sp);
if (struct_return)
regcache_cooked_write_unsigned (regcache,
- STRUCT_RETURN_REGNUM,
- struct_addr);
+ STRUCT_RETURN_REGNUM, struct_addr);
- /* Now make sure there's space on the stack */
- for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
- stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
- sp -= stack_alloc; /* make room on stack for args */
+ /* make room on stack for args */
+ sp -= sh_stack_allocsize (nargs, args);
+
+ /* Initialize float argument mechanism. */
+ sh_init_flt_argreg ();
/* Now load as many as possible of the first arguments into
registers, and push the rest onto the stack. There are 16 bytes
in four registers available. Loop thru args from first to last. */
-
- argreg = ARG0_REGNUM;
- flt_argreg = FLOAT_ARG0_REGNUM;
- for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
+ for (argnum = 0; argnum < nargs; argnum++)
{
type = VALUE_TYPE (args[argnum]);
len = TYPE_LENGTH (type);
- memset (valbuf, 0, sizeof (valbuf));
- if (len < 4)
- {
- /* value gets right-justified in the register or stack word */
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- memcpy (valbuf + (4 - len),
- (char *) VALUE_CONTENTS (args[argnum]), len);
- else
- memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
- val = valbuf;
- }
- else
- val = (char *) VALUE_CONTENTS (args[argnum]);
+ val = sh_justify_value_in_reg (args[argnum], len);
+
+ /* Some decisions have to be made how various types are handled.
+ This also differs in different ABIs. */
+ pass_on_stack = 0;
+
+ /* Find out the next register to use for a floating point value. */
+ treat_as_flt = sh_treat_as_flt_p (type);
+ if (treat_as_flt)
+ flt_argreg = sh_next_flt_argreg (len);
+ /* In contrast to non-FPU CPUs, arguments are never split between
+ registers and stack. If an argument doesn't fit in the remaining
+ registers it's always pushed entirely on the stack. */
+ else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
+ pass_on_stack = 1;
- if (len > 4 && (len & 3) != 0)
- odd_sized_struct = 1; /* Such structs go entirely on stack. */
- else if (len > 16)
- odd_sized_struct = 1; /* So do aggregates bigger than 4 words. */
- else
- odd_sized_struct = 0;
while (len > 0)
{
- if ((TYPE_CODE (type) == TYPE_CODE_FLT
- && flt_argreg > FLOAT_ARGLAST_REGNUM)
- || argreg > ARGLAST_REGNUM
- || odd_sized_struct)
- {
- /* must go on the stack */
- write_memory (sp + stack_offset, val, 4);
- stack_offset += 4;
+ if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
+ || (!treat_as_flt && (argreg > ARGLAST_REGNUM
+ || pass_on_stack)))
+ {
+ /* The data goes entirely on the stack, 4-byte aligned. */
+ reg_size = (len + 3) & ~3;
+ write_memory (sp + stack_offset, val, reg_size);
+ stack_offset += reg_size;
}
- /* NOTE WELL!!!!! This is not an "else if" clause!!!
- That's because some *&^%$ things get passed on the stack
- AND in the registers! */
- if (TYPE_CODE (type) == TYPE_CODE_FLT &&
- flt_argreg > 0 && flt_argreg <= FLOAT_ARGLAST_REGNUM)
+ else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
{
- /* Argument goes in a single-precision fp reg. */
- regval = extract_unsigned_integer (val, register_size (gdbarch,
- argreg));
+ /* Argument goes in a float argument register. */
+ reg_size = register_size (gdbarch, flt_argreg);
+ regval = extract_unsigned_integer (val, reg_size);
+ /* In little endian mode, float types taking two registers
+ (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
+ be stored swapped in the argument registers. The below
+ code first writes the first 32 bits in the next but one
+ register, increments the val and len values accordingly
+ and then proceeds as normal by writing the second 32 bits
+ into the next register. */
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
+ && TYPE_LENGTH (type) == 2 * reg_size)
+ {
+ regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
+ regval);
+ val += reg_size;
+ len -= reg_size;
+ regval = extract_unsigned_integer (val, reg_size);
+ }
regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
}
- else if (argreg <= ARGLAST_REGNUM)
- {
+ else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
+ {
/* there's room in a register */
- regval = extract_unsigned_integer (val, register_size (gdbarch,
- argreg));
+ reg_size = register_size (gdbarch, argreg);
+ regval = extract_unsigned_integer (val, reg_size);
regcache_cooked_write_unsigned (regcache, argreg++, regval);
}
- /* Store the value 4 bytes at a time. This means that things
- larger than 4 bytes may go partly in registers and partly
- on the stack. */
- len -= register_size (gdbarch, argreg);
- val += register_size (gdbarch, argreg);
+ /* Store the value one register at a time or in one step on stack. */
+ len -= reg_size;
+ val += reg_size;
}
}
}
static CORE_ADDR
-sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
+sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
CORE_ADDR func_addr,
- struct regcache *regcache,
- CORE_ADDR bp_addr,
- int nargs, struct value **args,
- CORE_ADDR sp, int struct_return,
+ struct regcache *regcache,
+ CORE_ADDR bp_addr,
+ int nargs, struct value **args,
+ CORE_ADDR sp, int struct_return,
CORE_ADDR struct_addr)
{
- int stack_offset, stack_alloc;
- int argreg;
+ int stack_offset = 0;
+ int argreg = ARG0_REGNUM;
int argnum;
struct type *type;
CORE_ADDR regval;
char *val;
- char valbuf[4];
- int len;
- int odd_sized_struct;
+ int len, reg_size;
/* first force sp to a 4-byte alignment */
sp = sh_frame_align (gdbarch, sp);
if (struct_return)
regcache_cooked_write_unsigned (regcache,
- STRUCT_RETURN_REGNUM,
- struct_addr);
+ STRUCT_RETURN_REGNUM, struct_addr);
- /* Now make sure there's space on the stack */
- for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
- stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
- sp -= stack_alloc; /* make room on stack for args */
+ /* make room on stack for args */
+ sp -= sh_stack_allocsize (nargs, args);
/* Now load as many as possible of the first arguments into
registers, and push the rest onto the stack. There are 16 bytes
in four registers available. Loop thru args from first to last. */
-
- argreg = ARG0_REGNUM;
- for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
+ for (argnum = 0; argnum < nargs; argnum++)
{
type = VALUE_TYPE (args[argnum]);
len = TYPE_LENGTH (type);
- memset (valbuf, 0, sizeof (valbuf));
- if (len < 4)
- {
- /* value gets right-justified in the register or stack word */
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- memcpy (valbuf + (4 - len),
- (char *) VALUE_CONTENTS (args[argnum]), len);
- else
- memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
- val = valbuf;
- }
- else
- val = (char *) VALUE_CONTENTS (args[argnum]);
+ val = sh_justify_value_in_reg (args[argnum], len);
- if (len > 4 && (len & 3) != 0)
- odd_sized_struct = 1; /* such structs go entirely on stack */
- else
- odd_sized_struct = 0;
while (len > 0)
{
- if (argreg > ARGLAST_REGNUM
- || odd_sized_struct)
- {
- /* must go on the stack */
- write_memory (sp + stack_offset, val, 4);
- stack_offset += 4;
+ if (argreg > ARGLAST_REGNUM)
+ {
+ /* The remainder of the data goes entirely on the stack,
+ 4-byte aligned. */
+ reg_size = (len + 3) & ~3;
+ write_memory (sp + stack_offset, val, reg_size);
+ stack_offset += reg_size;
}
- /* NOTE WELL!!!!! This is not an "else if" clause!!!
- That's because some *&^%$ things get passed on the stack
- AND in the registers! */
- if (argreg <= ARGLAST_REGNUM)
- {
+ else if (argreg <= ARGLAST_REGNUM)
+ {
/* there's room in a register */
- regval = extract_unsigned_integer (val, register_size (gdbarch,
- argreg));
+ reg_size = register_size (gdbarch, argreg);
+ regval = extract_unsigned_integer (val, reg_size);
regcache_cooked_write_unsigned (regcache, argreg++, regval);
}
- /* Store the value 4 bytes at a time. This means that things
- larger than 4 bytes may go partly in registers and partly
+ /* Store the value reg_size bytes at a time. This means that things
+ larger than reg_size bytes may go partly in registers and partly
on the stack. */
- len -= register_size (gdbarch, argreg);
- val += register_size (gdbarch, argreg);
+ len -= reg_size;
+ val += reg_size;
}
}
int len = TYPE_LENGTH (type);
int return_register = R0_REGNUM;
int offset;
-
+
if (len <= 4)
{
ULONGEST c;
{
int i, regnum = R0_REGNUM;
for (i = 0; i < len; i += 4)
- regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
+ regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
}
else
error ("bad size for return value");
sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
void *valbuf)
{
- if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ if (sh_treat_as_flt_p (type))
{
int len = TYPE_LENGTH (type);
int i, regnum = FP0_REGNUM;
for (i = 0; i < len; i += 4)
- regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
+ regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
+ else
+ regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
}
else
sh_default_extract_return_value (type, regcache, valbuf);
{
int i, regnum = R0_REGNUM;
for (i = 0; i < len; i += 4)
- regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
+ regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
}
}
sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
const void *valbuf)
{
- if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ if (sh_treat_as_flt_p (type))
{
int len = TYPE_LENGTH (type);
int i, regnum = FP0_REGNUM;
for (i = 0; i < len; i += 4)
- regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
+ regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
}
else
sh_default_store_return_value (type, regcache, valbuf);
(long) read_register (GBR_REGNUM),
(long) read_register (VBR_REGNUM));
- printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (0),
- (long) read_register (1),
- (long) read_register (2),
- (long) read_register (3),
- (long) read_register (4),
- (long) read_register (5),
- (long) read_register (6),
- (long) read_register (7));
+ printf_filtered
+ ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0), (long) read_register (1),
+ (long) read_register (2), (long) read_register (3),
+ (long) read_register (4), (long) read_register (5),
+ (long) read_register (6), (long) read_register (7));
printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (8),
- (long) read_register (9),
- (long) read_register (10),
- (long) read_register (11),
- (long) read_register (12),
- (long) read_register (13),
- (long) read_register (14),
- (long) read_register (15));
+ (long) read_register (8), (long) read_register (9),
+ (long) read_register (10), (long) read_register (11),
+ (long) read_register (12), (long) read_register (13),
+ (long) read_register (14), (long) read_register (15));
}
static void
(long) read_register (GBR_REGNUM),
(long) read_register (VBR_REGNUM));
printf_filtered (" SSR=%08lx SPC=%08lx",
- (long) read_register (SSR_REGNUM),
+ (long) read_register (SSR_REGNUM),
(long) read_register (SPC_REGNUM));
- printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (0),
- (long) read_register (1),
- (long) read_register (2),
- (long) read_register (3),
- (long) read_register (4),
- (long) read_register (5),
- (long) read_register (6),
- (long) read_register (7));
+ printf_filtered
+ ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0), (long) read_register (1),
+ (long) read_register (2), (long) read_register (3),
+ (long) read_register (4), (long) read_register (5),
+ (long) read_register (6), (long) read_register (7));
printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (8),
- (long) read_register (9),
- (long) read_register (10),
- (long) read_register (11),
- (long) read_register (12),
- (long) read_register (13),
- (long) read_register (14),
- (long) read_register (15));
+ (long) read_register (8), (long) read_register (9),
+ (long) read_register (10), (long) read_register (11),
+ (long) read_register (12), (long) read_register (13),
+ (long) read_register (14), (long) read_register (15));
}
(long) read_register (GBR_REGNUM),
(long) read_register (VBR_REGNUM));
printf_filtered (" FPUL=%08lx FPSCR=%08lx",
- (long) read_register (FPUL_REGNUM),
- (long) read_register (FPSCR_REGNUM));
-
- printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (0),
- (long) read_register (1),
- (long) read_register (2),
- (long) read_register (3),
- (long) read_register (4),
- (long) read_register (5),
- (long) read_register (6),
- (long) read_register (7));
+ (long) read_register (FPUL_REGNUM),
+ (long) read_register (FPSCR_REGNUM));
+
+ printf_filtered
+ ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0), (long) read_register (1),
+ (long) read_register (2), (long) read_register (3),
+ (long) read_register (4), (long) read_register (5),
+ (long) read_register (6), (long) read_register (7));
printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (8),
- (long) read_register (9),
- (long) read_register (10),
- (long) read_register (11),
- (long) read_register (12),
- (long) read_register (13),
- (long) read_register (14),
- (long) read_register (15));
-
- printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
- (long) read_register (FP0_REGNUM + 0),
- (long) read_register (FP0_REGNUM + 1),
- (long) read_register (FP0_REGNUM + 2),
- (long) read_register (FP0_REGNUM + 3),
- (long) read_register (FP0_REGNUM + 4),
- (long) read_register (FP0_REGNUM + 5),
- (long) read_register (FP0_REGNUM + 6),
- (long) read_register (FP0_REGNUM + 7));
- printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
- (long) read_register (FP0_REGNUM + 8),
- (long) read_register (FP0_REGNUM + 9),
- (long) read_register (FP0_REGNUM + 10),
- (long) read_register (FP0_REGNUM + 11),
- (long) read_register (FP0_REGNUM + 12),
- (long) read_register (FP0_REGNUM + 13),
- (long) read_register (FP0_REGNUM + 14),
- (long) read_register (FP0_REGNUM + 15));
+ (long) read_register (8), (long) read_register (9),
+ (long) read_register (10), (long) read_register (11),
+ (long) read_register (12), (long) read_register (13),
+ (long) read_register (14), (long) read_register (15));
+
+ printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
+ printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
}
static void
(long) read_register (FPUL_REGNUM),
(long) read_register (FPSCR_REGNUM));
- printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (0),
- (long) read_register (1),
- (long) read_register (2),
- (long) read_register (3),
- (long) read_register (4),
- (long) read_register (5),
- (long) read_register (6),
- (long) read_register (7));
+ printf_filtered
+ ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0), (long) read_register (1),
+ (long) read_register (2), (long) read_register (3),
+ (long) read_register (4), (long) read_register (5),
+ (long) read_register (6), (long) read_register (7));
printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (8),
- (long) read_register (9),
- (long) read_register (10),
- (long) read_register (11),
- (long) read_register (12),
- (long) read_register (13),
- (long) read_register (14),
- (long) read_register (15));
-
- printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
- (long) read_register (FP0_REGNUM + 0),
- (long) read_register (FP0_REGNUM + 1),
- (long) read_register (FP0_REGNUM + 2),
- (long) read_register (FP0_REGNUM + 3),
- (long) read_register (FP0_REGNUM + 4),
- (long) read_register (FP0_REGNUM + 5),
- (long) read_register (FP0_REGNUM + 6),
- (long) read_register (FP0_REGNUM + 7));
- printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
- (long) read_register (FP0_REGNUM + 8),
- (long) read_register (FP0_REGNUM + 9),
- (long) read_register (FP0_REGNUM + 10),
- (long) read_register (FP0_REGNUM + 11),
- (long) read_register (FP0_REGNUM + 12),
- (long) read_register (FP0_REGNUM + 13),
- (long) read_register (FP0_REGNUM + 14),
- (long) read_register (FP0_REGNUM + 15));
+ (long) read_register (8), (long) read_register (9),
+ (long) read_register (10), (long) read_register (11),
+ (long) read_register (12), (long) read_register (13),
+ (long) read_register (14), (long) read_register (15));
+
+ printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
+ printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
}
static void
(long) read_register (SSR_REGNUM),
(long) read_register (SPC_REGNUM));
- printf_filtered (" DSR=%08lx",
- (long) read_register (DSR_REGNUM));
-
- printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (0),
- (long) read_register (1),
- (long) read_register (2),
- (long) read_register (3),
- (long) read_register (4),
- (long) read_register (5),
- (long) read_register (6),
- (long) read_register (7));
+ printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
+
+ printf_filtered
+ ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0), (long) read_register (1),
+ (long) read_register (2), (long) read_register (3),
+ (long) read_register (4), (long) read_register (5),
+ (long) read_register (6), (long) read_register (7));
printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (8),
- (long) read_register (9),
- (long) read_register (10),
- (long) read_register (11),
- (long) read_register (12),
- (long) read_register (13),
- (long) read_register (14),
- (long) read_register (15));
-
- printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
- (long) read_register (A0G_REGNUM) & 0xff,
- (long) read_register (A0_REGNUM),
- (long) read_register (M0_REGNUM),
- (long) read_register (X0_REGNUM),
- (long) read_register (Y0_REGNUM),
- (long) read_register (RS_REGNUM),
- (long) read_register (MOD_REGNUM));
+ (long) read_register (8), (long) read_register (9),
+ (long) read_register (10), (long) read_register (11),
+ (long) read_register (12), (long) read_register (13),
+ (long) read_register (14), (long) read_register (15));
+
+ printf_filtered
+ ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
+ (long) read_register (A0G_REGNUM) & 0xff,
+ (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
+ (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
+ (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
(long) read_register (A1G_REGNUM) & 0xff,
(long) read_register (A1_REGNUM),
(long) read_register (FPUL_REGNUM),
(long) read_register (FPSCR_REGNUM));
- printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (0),
- (long) read_register (1),
- (long) read_register (2),
- (long) read_register (3),
- (long) read_register (4),
- (long) read_register (5),
- (long) read_register (6),
- (long) read_register (7));
+ printf_filtered
+ ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0), (long) read_register (1),
+ (long) read_register (2), (long) read_register (3),
+ (long) read_register (4), (long) read_register (5),
+ (long) read_register (6), (long) read_register (7));
printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (8),
- (long) read_register (9),
- (long) read_register (10),
- (long) read_register (11),
- (long) read_register (12),
- (long) read_register (13),
- (long) read_register (14),
- (long) read_register (15));
+ (long) read_register (8), (long) read_register (9),
+ (long) read_register (10), (long) read_register (11),
+ (long) read_register (12), (long) read_register (13),
+ (long) read_register (14), (long) read_register (15));
printf_filtered ((pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
- : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
+ :
+ "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
(long) read_register (FP0_REGNUM + 0),
(long) read_register (FP0_REGNUM + 1),
(long) read_register (FP0_REGNUM + 2),
(long) read_register (FP0_REGNUM + 5),
(long) read_register (FP0_REGNUM + 6),
(long) read_register (FP0_REGNUM + 7));
- printf_filtered ((pr
- ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
- : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
+ printf_filtered ((pr ?
+ "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
+ "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
(long) read_register (FP0_REGNUM + 8),
(long) read_register (FP0_REGNUM + 9),
(long) read_register (FP0_REGNUM + 10),
(long) read_register (FP0_REGNUM + 15));
}
+static void
+sh4_nofpu_show_regs (void)
+{
+ printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
+ paddr (read_register (PC_REGNUM)),
+ (long) read_register (SR_REGNUM),
+ (long) read_register (PR_REGNUM),
+ (long) read_register (MACH_REGNUM),
+ (long) read_register (MACL_REGNUM));
+
+ printf_filtered ("GBR=%08lx VBR=%08lx",
+ (long) read_register (GBR_REGNUM),
+ (long) read_register (VBR_REGNUM));
+ printf_filtered (" SSR=%08lx SPC=%08lx",
+ (long) read_register (SSR_REGNUM),
+ (long) read_register (SPC_REGNUM));
+
+ printf_filtered
+ ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0), (long) read_register (1),
+ (long) read_register (2), (long) read_register (3),
+ (long) read_register (4), (long) read_register (5),
+ (long) read_register (6), (long) read_register (7));
+ printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (8), (long) read_register (9),
+ (long) read_register (10), (long) read_register (11),
+ (long) read_register (12), (long) read_register (13),
+ (long) read_register (14), (long) read_register (15));
+}
+
static void
sh_dsp_show_regs (void)
{
(long) read_register (GBR_REGNUM),
(long) read_register (VBR_REGNUM));
- printf_filtered (" DSR=%08lx",
- (long) read_register (DSR_REGNUM));
-
- printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (0),
- (long) read_register (1),
- (long) read_register (2),
- (long) read_register (3),
- (long) read_register (4),
- (long) read_register (5),
- (long) read_register (6),
- (long) read_register (7));
+ printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
+
+ printf_filtered
+ ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0), (long) read_register (1),
+ (long) read_register (2), (long) read_register (3),
+ (long) read_register (4), (long) read_register (5),
+ (long) read_register (6), (long) read_register (7));
printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- (long) read_register (8),
- (long) read_register (9),
- (long) read_register (10),
- (long) read_register (11),
- (long) read_register (12),
- (long) read_register (13),
- (long) read_register (14),
- (long) read_register (15));
-
- printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
- (long) read_register (A0G_REGNUM) & 0xff,
- (long) read_register (A0_REGNUM),
- (long) read_register (M0_REGNUM),
- (long) read_register (X0_REGNUM),
- (long) read_register (Y0_REGNUM),
- (long) read_register (RS_REGNUM),
- (long) read_register (MOD_REGNUM));
+ (long) read_register (8), (long) read_register (9),
+ (long) read_register (10), (long) read_register (11),
+ (long) read_register (12), (long) read_register (13),
+ (long) read_register (14), (long) read_register (15));
+
+ printf_filtered
+ ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
+ (long) read_register (A0G_REGNUM) & 0xff,
+ (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
+ (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
+ (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
(long) read_register (A1G_REGNUM) & 0xff,
(long) read_register (A1_REGNUM),
sh_show_regs_command (char *args, int from_tty)
{
if (sh_show_regs)
- (*sh_show_regs)();
+ (*sh_show_regs) ();
}
/* Return the GDB type object for the "standard" data type
sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
{
if ((reg_nr >= FP0_REGNUM
- && (reg_nr <= FP_LAST_REGNUM))
- || (reg_nr == FPUL_REGNUM))
+ && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
return builtin_type_float;
else
return builtin_type_int;
sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
{
if ((reg_nr >= FP0_REGNUM
- && (reg_nr <= FP_LAST_REGNUM))
- || (reg_nr == FPUL_REGNUM))
+ && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
return builtin_type_float;
- else if (reg_nr >= DR0_REGNUM
- && reg_nr <= DR_LAST_REGNUM)
+ else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
return builtin_type_double;
- else if (reg_nr >= FV0_REGNUM
- && reg_nr <= FV_LAST_REGNUM)
+ else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
return sh_sh4_build_float_register_type (3);
else
return builtin_type_int;
static void
sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
- char *from, char *to)
+ char *from, char *to)
{
- if (regnum >= DR0_REGNUM
- && regnum <= DR_LAST_REGNUM)
+ if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
{
DOUBLEST val;
- floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
+ floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
+ from, &val);
store_typed_floating (to, type, val);
}
else
- error ("sh_register_convert_to_virtual called with non DR register number");
+ error
+ ("sh_register_convert_to_virtual called with non DR register number");
}
static void
sh_sh4_register_convert_to_raw (struct type *type, int regnum,
const void *from, void *to)
{
- if (regnum >= DR0_REGNUM
- && regnum <= DR_LAST_REGNUM)
+ if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
{
DOUBLEST val = extract_typed_floating (from, type);
- floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
+ floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
+ &val, to);
}
else
- error("sh_register_convert_to_raw called with non DR register number");
+ error ("sh_register_convert_to_raw called with non DR register number");
}
/* For vectors of 4 floating point registers. */
{
int fp_regnum;
- fp_regnum = FP0_REGNUM +
- (fv_regnum - FV0_REGNUM) * 4;
+ fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
return fp_regnum;
}
{
int fp_regnum;
- fp_regnum = FP0_REGNUM +
- (dr_regnum - DR0_REGNUM) * 2;
+ fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
return fp_regnum;
}
int base_regnum, portion;
char temp_buffer[MAX_REGISTER_SIZE];
- if (reg_nr >= DR0_REGNUM
- && reg_nr <= DR_LAST_REGNUM)
+ if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
{
base_regnum = dr_reg_base_num (reg_nr);
- /* Build the value in the provided buffer. */
+ /* Build the value in the provided buffer. */
/* Read the real regs for which this one is an alias. */
for (portion = 0; portion < 2; portion++)
- regcache_raw_read (regcache, base_regnum + portion,
+ regcache_raw_read (regcache, base_regnum + portion,
(temp_buffer
- + register_size (gdbarch, base_regnum) * portion));
+ + register_size (gdbarch,
+ base_regnum) * portion));
/* We must pay attention to the endiannes. */
sh_sh4_register_convert_to_virtual (reg_nr,
- gdbarch_register_type (gdbarch, reg_nr),
+ gdbarch_register_type (gdbarch,
+ reg_nr),
temp_buffer, buffer);
}
- else if (reg_nr >= FV0_REGNUM
- && reg_nr <= FV_LAST_REGNUM)
+ else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
{
base_regnum = fv_reg_base_num (reg_nr);
/* Read the real regs for which this one is an alias. */
for (portion = 0; portion < 4; portion++)
- regcache_raw_read (regcache, base_regnum + portion,
+ regcache_raw_read (regcache, base_regnum + portion,
((char *) buffer
- + register_size (gdbarch, base_regnum) * portion));
+ + register_size (gdbarch,
+ base_regnum) * portion));
}
}
int base_regnum, portion;
char temp_buffer[MAX_REGISTER_SIZE];
- if (reg_nr >= DR0_REGNUM
- && reg_nr <= DR_LAST_REGNUM)
+ if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
{
base_regnum = dr_reg_base_num (reg_nr);
/* We must pay attention to the endiannes. */
- sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), reg_nr,
- buffer, temp_buffer);
+ sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
+ reg_nr, buffer, temp_buffer);
/* Write the real regs for which this one is an alias. */
for (portion = 0; portion < 2; portion++)
- regcache_raw_write (regcache, base_regnum + portion,
+ regcache_raw_write (regcache, base_regnum + portion,
(temp_buffer
- + register_size (gdbarch, base_regnum) * portion));
+ + register_size (gdbarch,
+ base_regnum) * portion));
}
- else if (reg_nr >= FV0_REGNUM
- && reg_nr <= FV_LAST_REGNUM)
+ else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
{
base_regnum = fv_reg_base_num (reg_nr);
for (portion = 0; portion < 4; portion++)
regcache_raw_write (regcache, base_regnum + portion,
((char *) buffer
- + register_size (gdbarch, base_regnum) * portion));
+ + register_size (gdbarch,
+ base_regnum) * portion));
}
}
int fv_regnum)
{
int first_fp_reg_num = fv_reg_base_num (fv_regnum);
- fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
- fv_regnum - FV0_REGNUM,
- (int) read_register (first_fp_reg_num),
- (int) read_register (first_fp_reg_num + 1),
- (int) read_register (first_fp_reg_num + 2),
- (int) read_register (first_fp_reg_num + 3));
+ fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
+ fv_regnum - FV0_REGNUM,
+ (int) read_register (first_fp_reg_num),
+ (int) read_register (first_fp_reg_num + 1),
+ (int) read_register (first_fp_reg_num + 2),
+ (int) read_register (first_fp_reg_num + 3));
}
/* Double precision registers. */
{
int first_fp_reg_num = dr_reg_base_num (dr_regnum);
- fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
- dr_regnum - DR0_REGNUM,
+ fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
+ dr_regnum - DR0_REGNUM,
(int) read_register (first_fp_reg_num),
(int) read_register (first_fp_reg_num + 1));
}
if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
internal_error (__FILE__, __LINE__,
"Invalid pseudo register number %d\n", regnum);
- else if (regnum >= DR0_REGNUM
- && regnum <= DR_LAST_REGNUM)
+ else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
do_dr_register_info (gdbarch, file, regnum);
- else if (regnum >= FV0_REGNUM
- && regnum <= FV_LAST_REGNUM)
+ else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
do_fv_register_info (gdbarch, file, regnum);
}
sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
{ /* do values for FP (float) regs */
char *raw_buffer;
- double flt; /* double extracted from raw hex data */
+ double flt; /* double extracted from raw hex data */
int inv;
int j;
if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
- /* Get the register as a number */
+ /* Get the register as a number */
flt = unpack_double (builtin_type_float, raw_buffer, &inv);
/* Print the name and some spaces. */
fprintf_filtered (file, "\t(raw 0x");
for (j = 0; j < register_size (gdbarch, regnum); j++)
{
- register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
- : register_size (gdbarch, regnum) - 1 - j;
+ int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+ ? j
+ : register_size (gdbarch, regnum) - 1 - j);
fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
}
fprintf_filtered (file, ")");
/* Get the data in raw format. */
if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
fprintf_filtered (file, "*value not available*\n");
-
+
val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
file, 'x', 1, 0, Val_pretty_default);
fprintf_filtered (file, "\t");
else if (regnum >= 0 && regnum < NUM_REGS)
{
- if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
+ if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
+ TYPE_CODE_FLT)
sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
else
sh_do_register (gdbarch, file, regnum); /* All other regs */
processor, so don't display anything. */
if (REGISTER_NAME (regnum) == NULL
|| *(REGISTER_NAME (regnum)) == '\0')
- {
+ {
regnum++;
continue;
}
- if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
+ if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
+ TYPE_CODE_FLT)
{
if (fpregs)
{
/* true for "INFO ALL-REGISTERS" command */
sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
- regnum ++;
+ regnum++;
}
else
regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
lmo.r_debug_size = 8; /* 20 not actual size but all we need */
lmo.r_map_offset = 4;
- lmo.r_map_size = 4;
+ lmo.r_map_size = 4;
lmo.link_map_size = 20; /* 552 not actual size but all we need */
lmo.l_addr_offset = 0;
- lmo.l_addr_size = 4;
+ lmo.l_addr_size = 4;
lmo.l_name_offset = 4;
- lmo.l_name_size = 4;
+ lmo.l_name_size = 4;
lmo.l_next_offset = 12;
- lmo.l_next_size = 4;
+ lmo.l_next_size = 4;
lmo.l_prev_offset = 16;
- lmo.l_prev_size = 4;
+ lmo.l_prev_size = 4;
}
- return lmp;
+ return lmp;
}
#endif /* SVR4_SHARED_LIBS */
/* Frameless until proven otherwise. */
cache->uses_fp = 0;
-
+
/* Saved registers. We initialize these to -1 since zero is a valid
offset (that's where fp is supposed to be stored). */
for (i = 0; i < SH_NUM_REGS; i++)
{
cache->saved_regs[i] = -1;
}
-
+
return cache;
-}
+}
static struct sh_frame_cache *
sh_frame_cache (struct frame_info *next_frame, void **this_cache)
current_pc = frame_pc_unwind (next_frame);
if (cache->pc != 0)
sh_analyze_prologue (cache->pc, current_pc, cache);
-
+
if (!cache->uses_fp)
{
/* We didn't find a valid frame, which means that CACHE->base
*addrp = 0;
*realnump = -1;
if (valuep)
- {
- /* Store the value. */
- store_unsigned_integer (valuep, 4, cache->saved_sp);
- }
+ {
+ /* Store the value. */
+ store_unsigned_integer (valuep, 4, cache->saved_sp);
+ }
return;
}
*addrp = cache->saved_regs[regnum];
*realnump = -1;
if (valuep)
- {
- /* Read the value in from memory. */
- read_memory (*addrp, valuep,
- register_size (current_gdbarch, regnum));
- }
+ {
+ /* Read the value in from memory. */
+ read_memory (*addrp, valuep,
+ register_size (current_gdbarch, regnum));
+ }
return;
}
frame_register_unwind (next_frame, regnum,
- optimizedp, lvalp, addrp, realnump, valuep);
+ optimizedp, lvalp, addrp, realnump, valuep);
}
static void
sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
- struct frame_id *this_id)
-{
+ struct frame_id *this_id)
+{
struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
/* This marks the outermost frame. */
return;
*this_id = frame_id_build (cache->saved_sp, cache->pc);
-}
+}
-static const struct frame_unwind sh_frame_unwind =
-{
+static const struct frame_unwind sh_frame_unwind = {
NORMAL_FRAME,
sh_frame_this_id,
sh_frame_prev_register
static CORE_ADDR
sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
-{
+{
struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
-
+
return cache->base;
}
-
-static const struct frame_base sh_frame_base =
-{
+
+static const struct frame_base sh_frame_base = {
&sh_frame_unwind,
sh_frame_base_address,
sh_frame_base_address,
sh_frame_base_address
-};
+};
/* The epilogue is defined here as the area at the end of a function,
either on the `ret' instruction itself or after an instruction which
ULONGEST inst;
/* The sh epilogue is max. 14 bytes long. Give another 14 bytes
for a nop and some fixed data (e.g. big offsets) which are
- unfortunately also treated as part of the function (which
- means, they are below func_end. */
+ unfortunately also treated as part of the function (which
+ means, they are below func_end. */
CORE_ADDR addr = func_end - 28;
if (addr < func_addr + 4)
- addr = func_addr + 4;
+ addr = func_addr + 4;
if (pc < addr)
return 0;
/* First search forward until hitting an rts. */
while (addr < func_end
- && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
+ && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
addr += 2;
if (addr >= func_end)
- return 0;
+ return 0;
/* At this point we should find a mov.l @r15+,r14 instruction,
either before or after the rts. If not, then the function has
- probably no "normal" epilogue and we bail out here. */
+ probably no "normal" epilogue and we bail out here. */
inst = read_memory_unsigned_integer (addr - 2, 2);
if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
- addr -= 2;
+ addr -= 2;
else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
return 0;
/* Step over possible lds.l @r15+,pr. */
inst = read_memory_unsigned_integer (addr - 2, 2);
if (IS_LDS (inst))
- {
+ {
addr -= 2;
inst = read_memory_unsigned_integer (addr - 2, 2);
}
/* Step over possible mov r14,r15. */
if (IS_MOV_FP_SP (inst))
- {
+ {
addr -= 2;
inst = read_memory_unsigned_integer (addr - 2, 2);
}
/* Now check for FP adjustments, using add #imm,r14 or add rX, r14
instructions. */
while (addr > func_addr + 4
- && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
+ && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
{
addr -= 2;
inst = read_memory_unsigned_integer (addr - 2, 2);
sh_show_regs = sh_generic_show_regs;
switch (info.bfd_arch_info->mach)
{
- case bfd_mach_sh2e:
- sh_show_regs = sh2e_show_regs;
- break;
- case bfd_mach_sh_dsp:
- sh_show_regs = sh_dsp_show_regs;
- break;
+ case bfd_mach_sh2e:
+ sh_show_regs = sh2e_show_regs;
+ break;
+ case bfd_mach_sh_dsp:
+ sh_show_regs = sh_dsp_show_regs;
+ break;
- case bfd_mach_sh3:
- sh_show_regs = sh3_show_regs;
- break;
+ case bfd_mach_sh3:
+ sh_show_regs = sh3_show_regs;
+ break;
- case bfd_mach_sh3e:
- sh_show_regs = sh3e_show_regs;
- break;
+ case bfd_mach_sh3e:
+ sh_show_regs = sh3e_show_regs;
+ break;
- case bfd_mach_sh3_dsp:
- sh_show_regs = sh3_dsp_show_regs;
- break;
+ case bfd_mach_sh3_dsp:
+ case bfd_mach_sh4al_dsp:
+ sh_show_regs = sh3_dsp_show_regs;
+ break;
- case bfd_mach_sh4:
- sh_show_regs = sh4_show_regs;
- break;
+ case bfd_mach_sh4:
+ case bfd_mach_sh4a:
+ sh_show_regs = sh4_show_regs;
+ break;
+
+ case bfd_mach_sh4_nofpu:
+ case bfd_mach_sh4a_nofpu:
+ sh_show_regs = sh4_nofpu_show_regs;
+ break;
- case bfd_mach_sh5:
- sh_show_regs = sh64_show_regs;
- /* SH5 is handled entirely in sh64-tdep.c */
- return sh64_gdbarch_init (info, arches);
+ case bfd_mach_sh5:
+ sh_show_regs = sh64_show_regs;
+ /* SH5 is handled entirely in sh64-tdep.c */
+ return sh64_gdbarch_init (info, arches);
}
/* If there is already a candidate, use it. */
set_gdbarch_decr_pc_after_break (gdbarch, 0);
set_gdbarch_function_start_offset (gdbarch, 0);
- set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
set_gdbarch_frame_args_skip (gdbarch, 0);
set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
frame_base_set_default (gdbarch, &sh_frame_base);
- set_gdbarch_in_function_epilogue_p (gdbarch,
- sh_in_function_epilogue_p);
+ set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
switch (info.bfd_arch_info->mach)
{
case bfd_mach_sh2:
set_gdbarch_register_name (gdbarch, sh_sh_register_name);
- break;
+ break;
case bfd_mach_sh2e:
/* doubles on sh2e and sh3e are actually 4 byte. */
set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
set_gdbarch_fp0_regnum (gdbarch, 25);
set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
- set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
+ set_gdbarch_extract_return_value (gdbarch,
+ sh3e_sh4_extract_return_value);
set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
break;
set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
set_gdbarch_fp0_regnum (gdbarch, 25);
set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
- set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
+ set_gdbarch_extract_return_value (gdbarch,
+ sh3e_sh4_extract_return_value);
set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
break;
break;
case bfd_mach_sh4:
+ case bfd_mach_sh4a:
set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
set_gdbarch_fp0_regnum (gdbarch, 25);
set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
- set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
+ set_gdbarch_extract_return_value (gdbarch,
+ sh3e_sh4_extract_return_value);
set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
break;
+ case bfd_mach_sh4_nofpu:
+ case bfd_mach_sh4a_nofpu:
+ set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
+ break;
+
+ case bfd_mach_sh4al_dsp:
+ set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
+ set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
+ break;
+
default:
set_gdbarch_register_name (gdbarch, sh_generic_register_name);
break;
return gdbarch;
}
-extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
+extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
void
_initialize_sh_tdep (void)
{
struct cmd_list_element *c;
-
+
gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
projects / deliverable / binutils-gdb.git / blobdiff