/* Target-dependent code for Renesas Super-H, for GDB.
Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
+ 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
This file is part of GDB.
};
static const char *
-sh_sh_register_name (int reg_nr)
+sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
}
static const char *
-sh_sh3_register_name (int reg_nr)
+sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
}
static const char *
-sh_sh3e_register_name (int reg_nr)
+sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
}
static const char *
-sh_sh2e_register_name (int reg_nr)
+sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
}
static const char *
-sh_sh2a_register_name (int reg_nr)
+sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
/* general registers 0-15 */
}
static const char *
-sh_sh2a_nofpu_register_name (int reg_nr)
+sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
/* general registers 0-15 */
}
static const char *
-sh_sh_dsp_register_name (int reg_nr)
+sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
}
static const char *
-sh_sh3_dsp_register_name (int reg_nr)
+sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
}
static const char *
-sh_sh4_register_name (int reg_nr)
+sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
/* general registers 0-15 */
}
static const char *
-sh_sh4_nofpu_register_name (int reg_nr)
+sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
/* general registers 0-15 */
}
static const char *
-sh_sh4al_dsp_register_name (int reg_nr)
+sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
}
static const unsigned char *
-sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
+sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
{
/* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
static unsigned char breakpoint[] = { 0xc3, 0xc3 };
static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
*lenptr = sizeof (big_remote_breakpoint);
return big_remote_breakpoint;
/* Helper function to justify value in register according to endianess. */
static char *
-sh_justify_value_in_reg (struct value *val, int len)
+sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
{
static char valbuf[4];
if (len < 4)
{
/* value gets right-justified in the register or stack word */
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
else
memcpy (valbuf, (char *) value_contents (val), len);
29) the parity of the register number is preserved, which is important
for the double register passing test (see the "argreg & 1" test below). */
static int
-sh_next_flt_argreg (int len)
+sh_next_flt_argreg (struct gdbarch *gdbarch, int len)
{
int argreg;
/* Also mark the next register as used. */
flt_argreg_array[argreg + 1] = 1;
}
- else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
{
/* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
if (!flt_argreg_array[argreg + 1])
{
type = value_type (args[argnum]);
len = TYPE_LENGTH (type);
- val = sh_justify_value_in_reg (args[argnum], len);
+ val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
/* Some decisions have to be made how various types are handled.
This also differs in different ABIs. */
/* Find out the next register to use for a floating point value. */
treat_as_flt = sh_treat_as_flt_p (type);
if (treat_as_flt)
- flt_argreg = sh_next_flt_argreg (len);
+ flt_argreg = sh_next_flt_argreg (gdbarch, len);
/* In contrast to non-FPU CPUs, arguments are never split between
registers and stack. If an argument doesn't fit in the remaining
registers it's always pushed entirely on the stack. */
{
type = value_type (args[argnum]);
len = TYPE_LENGTH (type);
- val = sh_justify_value_in_reg (args[argnum], len);
+ val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
while (len > 0)
{
sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
void *valbuf)
{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
if (sh_treat_as_flt_p (type))
{
int len = TYPE_LENGTH (type);
- int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
+ int i, regnum = gdbarch_fp0_regnum (gdbarch);
for (i = 0; i < len; i += 4)
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
else
regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
const void *valbuf)
{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
if (sh_treat_as_flt_p (type))
{
int len = TYPE_LENGTH (type);
- int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
+ int i, regnum = gdbarch_fp0_regnum (gdbarch);
for (i = 0; i < len; i += 4)
- if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
regcache_raw_write (regcache, regnum++,
(char *) valbuf + len - 4 - i);
else
/* For vectors of 4 floating point registers. */
static int
-fv_reg_base_num (int fv_regnum)
+fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
{
int fp_regnum;
- fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
+ fp_regnum = gdbarch_fp0_regnum (gdbarch)
+ (fv_regnum - FV0_REGNUM) * 4;
return fp_regnum;
}
/* For double precision floating point registers, i.e 2 fp regs.*/
static int
-dr_reg_base_num (int dr_regnum)
+dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
{
int fp_regnum;
- fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
+ fp_regnum = gdbarch_fp0_regnum (gdbarch)
+ (dr_regnum - DR0_REGNUM) * 2;
return fp_regnum;
}
else
if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
{
- base_regnum = dr_reg_base_num (reg_nr);
+ base_regnum = dr_reg_base_num (gdbarch, reg_nr);
/* Build the value in the provided buffer. */
/* Read the real regs for which this one is an alias. */
}
else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
{
- base_regnum = fv_reg_base_num (reg_nr);
+ base_regnum = fv_reg_base_num (gdbarch, reg_nr);
/* Read the real regs for which this one is an alias. */
for (portion = 0; portion < 4; portion++)
}
else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
{
- base_regnum = dr_reg_base_num (reg_nr);
+ base_regnum = dr_reg_base_num (gdbarch, reg_nr);
/* We must pay attention to the endiannes. */
sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
}
else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
{
- base_regnum = fv_reg_base_num (reg_nr);
+ base_regnum = fv_reg_base_num (gdbarch, reg_nr);
/* Write the real regs for which this one is an alias. */
for (portion = 0; portion < 4; portion++)
}
static int
-sh_dsp_register_sim_regno (int nr)
+sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
{
- if (legacy_register_sim_regno (nr) < 0)
- return legacy_register_sim_regno (nr);
+ if (legacy_register_sim_regno (gdbarch, nr) < 0)
+ return legacy_register_sim_regno (gdbarch, nr);
if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
if (nr == MOD_REGNUM)
}
static int
-sh_sh2a_register_sim_regno (int nr)
+sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
{
switch (nr)
{
default:
break;
}
- return legacy_register_sim_regno (nr);
+ return legacy_register_sim_regno (gdbarch, nr);
}
/* Set up the register unwinding such that call-clobbered registers are