/* Target-dependent code for the SPARC for GDB, the GNU debugger.
- Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994
+ Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997
Free Software Foundation, Inc.
This file is part of GDB.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
-Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Support for calling functions from gdb in sparc64 is unfinished. */
#include "defs.h"
#include "frame.h"
#include "obstack.h"
#include "target.h"
#include "value.h"
+#include "bfd.h"
+#include "gdb_string.h"
#ifdef USE_PROC_FS
#include <sys/procfs.h>
#include "gdbcore.h"
+#if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
+#define SPARC_HAS_FPU 0
+#else
+#define SPARC_HAS_FPU 1
+#endif
+
+#ifdef GDB_TARGET_IS_SPARC64
+#define FP_REGISTER_BYTES (64 * 4)
+#else
+#define FP_REGISTER_BYTES (32 * 4)
+#endif
+
+/* If not defined, assume 32 bit sparc. */
+#ifndef FP_MAX_REGNUM
+#define FP_MAX_REGNUM (FP0_REGNUM + 32)
+#endif
+
+#define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
+
/* From infrun.c */
extern int stop_after_trap;
int deferred_stores = 0; /* Cumulates stores we want to do eventually. */
+
+/* Fetch a single instruction. Even on bi-endian machines
+ such as sparc86x, instructions are always big-endian. */
+
+static unsigned long
+fetch_instruction (pc)
+ CORE_ADDR pc;
+{
+ unsigned long retval;
+ int i;
+ unsigned char buf[4];
+
+ read_memory (pc, buf, sizeof (buf));
+
+ /* Start at the most significant end of the integer, and work towards
+ the least significant. */
+ retval = 0;
+ for (i = 0; i < sizeof (buf); ++i)
+ retval = (retval << 8) | buf[i];
+ return retval;
+}
+
+
+/* Branches with prediction are treated like their non-predicting cousins. */
+/* FIXME: What about floating point branches? */
+
/* Macros to extract fields from sparc instructions. */
#define X_OP(i) (((i) >> 30) & 0x3)
#define X_RD(i) (((i) >> 25) & 0x1f)
/* Sign extension macros. */
#define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
+#define X_CC(i) (((i) >> 20) & 3)
+#define X_P(i) (((i) >> 19) & 1)
+#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
+#define X_RCOND(i) (((i) >> 25) & 7)
+#define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
+#define X_FCN(i) (((i) >> 25) & 31)
typedef enum
{
- Error, not_branch, bicc, bicca, ba, baa, ticc, ta
+ Error, not_branch, bicc, bicca, ba, baa, ticc, ta,
+#ifdef GDB_TARGET_IS_SPARC64
+ done_retry
+#endif
} branch_type;
/* Simulate single-step ptrace call for sun4. Code written by Gary
int one_stepped;
+static branch_type isbranch PARAMS ((long, CORE_ADDR, CORE_ADDR *));
+
/* single_step() is called just before we want to resume the inferior,
if we want to single-step it but there is no hardware or kernel single-step
support (as on all SPARCs). We find all the possible targets of the
void
single_step (ignore)
- int ignore; /* pid, but we don't need it */
+ enum target_signal ignore; /* pid, but we don't need it */
{
- branch_type br, isannulled();
+ branch_type br;
CORE_ADDR pc;
long pc_instruction;
/* printf_unfiltered ("set break at %x\n",next_pc); */
pc = read_register (PC_REGNUM);
- pc_instruction = read_memory_integer (pc, 4);
- br = isannulled (pc_instruction, pc, &target);
+ pc_instruction = fetch_instruction (pc);
+ br = isbranch (pc_instruction, pc, &target);
brknpc4 = brktrg = 0;
if (br == bicca)
brktrg = 1;
target_insert_breakpoint (target, break_mem[2]);
}
+#ifdef GDB_TARGET_IS_SPARC64
+ else if (br == done_retry)
+ {
+ brktrg = 1;
+ target_insert_breakpoint (target, break_mem[2]);
+ }
+#endif
/* We are ready to let it go */
one_stepped = 1;
fi->bottom =
(fi->next ?
(fi->frame == fi->next->frame ? fi->next->bottom : fi->next->frame) :
- read_register (SP_REGNUM));
+ read_sp ());
/* If fi->next is NULL, then we already set ->frame by passing read_fp()
to create_new_frame. */
if (fi->next)
{
char buf[MAX_REGISTER_RAW_SIZE];
- int err;
/* Compute ->frame as if not flat. If it is flat, we'll change
it later. */
- /* FIXME: If error reading memory, should just stop backtracing, rather
- than error(). */
- get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0);
- fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM));
+ if (fi->next->next != NULL
+ && (fi->next->next->signal_handler_caller
+ || frame_in_dummy (fi->next->next))
+ && frameless_look_for_prologue (fi->next))
+ {
+ /* A frameless function interrupted by a signal did not change
+ the frame pointer, fix up frame pointer accordingly. */
+ fi->frame = FRAME_FP (fi->next);
+ fi->bottom = fi->next->bottom;
+ }
+ else
+ {
+ /* Should we adjust for stack bias here? */
+ get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0);
+ fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM));
+#ifdef GDB_TARGET_IS_SPARC64
+ if (fi->frame & 1)
+ fi->frame += 2047;
+#endif
+
+ }
}
/* Decide whether this is a function with a ``flat register window''
negative number if a flat frame) to the sp. FIXME: Does not
handle large frames which will need more than one instruction
to adjust the sp. */
- insn = read_memory_integer (addr, 4);
+ insn = fetch_instruction (addr);
if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0
&& X_I (insn) && X_SIMM13 (insn) < 0)
{
int offset = X_SIMM13 (insn);
/* Then look for a save of %i7 into the frame. */
- insn = read_memory_integer (addr + 4, 4);
+ insn = fetch_instruction (addr + 4);
if (X_OP (insn) == 3
&& X_RD (insn) == 31
&& X_OP3 (insn) == 4
/* Overwrite the frame's address with the value in %i7. */
get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0);
fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM));
-
+#ifdef GDB_TARGET_IS_SPARC64
+ if (fi->frame & 1)
+ fi->frame += 2047;
+#endif
/* Record where the fp got saved. */
fi->fp_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn);
/* Also try to collect where the pc got saved to. */
fi->pc_addr = 0;
- insn = read_memory_integer (addr + 12, 4);
+ insn = fetch_instruction (addr + 12);
if (X_OP (insn) == 3
&& X_RD (insn) == 15
&& X_OP3 (insn) == 4
sparc_extract_struct_value_address (regbuf)
char regbuf[REGISTER_BYTES];
{
- return read_memory_integer (((int *)(regbuf))[SP_REGNUM]+(16*4),
+#ifdef GDB_TARGET_IS_SPARC64
+ return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM),
+ REGISTER_RAW_SIZE (O0_REGNUM));
+#else
+ CORE_ADDR sp = extract_address (®buf [REGISTER_BYTE (SP_REGNUM)],
+ REGISTER_RAW_SIZE (SP_REGNUM));
+ return read_memory_integer (sp + (16 * SPARC_INTREG_SIZE),
TARGET_PTR_BIT / TARGET_CHAR_BIT);
+#endif
}
/* Find the pc saved in frame FRAME. */
/* The sigcontext address is contained in register O2. */
get_saved_register (buf, (int *)NULL, (CORE_ADDR *)NULL,
frame, O0_REGNUM + 2, (enum lval_type *)NULL);
- sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM));
+ sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2));
/* Don't cause a memory_error when accessing sigcontext in case the
stack layout has changed or the stack is corrupt. */
scbuf, sizeof (scbuf));
return extract_address (scbuf, sizeof (scbuf));
}
+ else if (frame->next != NULL
+ && (frame->next->signal_handler_caller
+ || frame_in_dummy (frame->next))
+ && frameless_look_for_prologue (frame))
+ {
+ /* A frameless function interrupted by a signal did not save
+ the PC, it is still in %o7. */
+ get_saved_register (buf, (int *)NULL, (CORE_ADDR *)NULL,
+ frame, O7_REGNUM, (enum lval_type *)NULL);
+ return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE));
+ }
if (frame->flat)
addr = frame->pc_addr;
else
addr = frame->bottom + FRAME_SAVED_I0 +
- REGISTER_RAW_SIZE (I7_REGNUM) * (I7_REGNUM - I0_REGNUM);
+ SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM);
if (addr == 0)
/* A flat frame leaf function might not save the PC anywhere,
just leave it in %o7. */
return PC_ADJUST (read_register (O7_REGNUM));
- read_memory (addr, buf, REGISTER_RAW_SIZE (I7_REGNUM));
- return PC_ADJUST (extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM)));
+ read_memory (addr, buf, SPARC_INTREG_SIZE);
+ return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE));
}
/* Since an individual frame in the frame cache is defined by two
CORE_ADDR pc = start_pc;
int is_flat = 0;
- insn = read_memory_integer (pc, 4);
+ insn = fetch_instruction (pc);
/* Recognize the `sethi' insn and record its destination. */
if (X_OP (insn) == 0 && X_OP2 (insn) == 4)
{
dest = X_RD (insn);
pc += 4;
- insn = read_memory_integer (pc, 4);
+ insn = fetch_instruction (pc);
}
/* Recognize an add immediate value to register to either %g1 or
&& (X_RD (insn) == 1 || X_RD (insn) == dest))
{
pc += 4;
- insn = read_memory_integer (pc, 4);
+ insn = fetch_instruction (pc);
}
/* Recognize any SAVE insn. */
pc += 4;
if (frameless_p) /* If the save is all we care about, */
return pc; /* return before doing more work */
- insn = read_memory_integer (pc, 4);
+ insn = fetch_instruction (pc);
}
/* Recognize add to %sp. */
else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0)
if (frameless_p) /* If the add is all we care about, */
return pc; /* return before doing more work */
is_flat = 1;
- insn = read_memory_integer (pc, 4);
+ insn = fetch_instruction (pc);
/* Recognize store of frame pointer (i7). */
if (X_OP (insn) == 3
&& X_RD (insn) == 31
&& X_RS1 (insn) == 14)
{
pc += 4;
- insn = read_memory_integer (pc, 4);
+ insn = fetch_instruction (pc);
/* Recognize sub %sp, <anything>, %i7. */
if (X_OP (insn) == 2
&& X_RD (insn) == 31)
{
pc += 4;
- insn = read_memory_integer (pc, 4);
+ insn = fetch_instruction (pc);
}
else
return pc;
else
break;
pc += 4;
- insn = read_memory_integer (pc, 4);
+ insn = fetch_instruction (pc);
}
return pc;
return examine_prologue (start_pc, frameless_p, NULL, NULL);
}
-/* Check instruction at ADDR to see if it is an annulled branch.
- All other instructions will go to NPC or will trap.
- Set *TARGET if we find a candidate branch; set to zero if not. */
-
-branch_type
-isannulled (instruction, addr, target)
+/* Check instruction at ADDR to see if it is a branch.
+ All non-annulled instructions will go to NPC or will trap.
+ Set *TARGET if we find a candidate branch; set to zero if not.
+
+ This isn't static as it's used by remote-sa.sparc.c. */
+
+static branch_type
+isbranch (instruction, addr, target)
long instruction;
CORE_ADDR addr, *target;
{
branch_type val = not_branch;
- long int offset; /* Must be signed for sign-extend. */
+ long int offset = 0; /* Must be signed for sign-extend. */
*target = 0;
if (X_OP (instruction) == 0
&& (X_OP2 (instruction) == 2
|| X_OP2 (instruction) == 6
- || X_OP2 (instruction) == 7))
+ || X_OP2 (instruction) == 1
+ || X_OP2 (instruction) == 3
+ || X_OP2 (instruction) == 5
+#ifndef GDB_TARGET_IS_SPARC64
+ || X_OP2 (instruction) == 7
+#endif
+ ))
{
if (X_COND (instruction) == 8)
val = X_A (instruction) ? baa : ba;
else
val = X_A (instruction) ? bicca : bicc;
- offset = 4 * X_DISP22 (instruction);
+ switch (X_OP2 (instruction))
+ {
+ case 2:
+ case 6:
+#ifndef GDB_TARGET_IS_SPARC64
+ case 7:
+#endif
+ offset = 4 * X_DISP22 (instruction);
+ break;
+ case 1:
+ case 5:
+ offset = 4 * X_DISP19 (instruction);
+ break;
+ case 3:
+ offset = 4 * X_DISP16 (instruction);
+ break;
+ }
*target = addr + offset;
}
+#ifdef GDB_TARGET_IS_SPARC64
+ else if (X_OP (instruction) == 2
+ && X_OP3 (instruction) == 62)
+ {
+ if (X_FCN (instruction) == 0)
+ {
+ /* done */
+ *target = read_register (TNPC_REGNUM);
+ val = done_retry;
+ }
+ else if (X_FCN (instruction) == 1)
+ {
+ /* retry */
+ *target = read_register (TPC_REGNUM);
+ val = done_retry;
+ }
+ }
+#endif
return val;
}
struct frame_info *frame1;
CORE_ADDR addr;
+ if (!target_has_registers)
+ error ("No registers.");
+
if (optimized)
*optimized = 0;
addr = 0;
+
+ /* FIXME This code extracted from infcmd.c; should put elsewhere! */
+ if (frame == NULL)
+ {
+ /* error ("No selected frame."); */
+ if (!target_has_registers)
+ error ("The program has no registers now.");
+ if (selected_frame == NULL)
+ error ("No selected frame.");
+ /* Try to use selected frame */
+ frame = get_prev_frame (selected_frame);
+ if (frame == 0)
+ error ("Cmd not meaningful in the outermost frame.");
+ }
+
+
frame1 = frame->next;
+
+ /* Get saved PC from the frame info if not in innermost frame. */
+ if (regnum == PC_REGNUM && frame1 != NULL)
+ {
+ if (lval != NULL)
+ *lval = not_lval;
+ if (raw_buffer != NULL)
+ {
+ /* Put it back in target format. */
+ store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), frame->pc);
+ }
+ if (addrp != NULL)
+ *addrp = 0;
+ return;
+ }
+
while (frame1 != NULL)
{
if (frame1->pc >= (frame1->bottom ? frame1->bottom :
- read_register (SP_REGNUM))
+ read_sp ())
&& frame1->pc <= FRAME_FP (frame1))
{
- /* Dummy frame. All but the window regs are in there somewhere. */
+ /* Dummy frame. All but the window regs are in there somewhere.
+ The window registers are saved on the stack, just like in a
+ normal frame. */
if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7)
- addr = frame1->frame + (regnum - G0_REGNUM) * 4 - 0xa0;
+ addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE
+ - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE);
else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8)
- addr = frame1->frame + (regnum - I0_REGNUM) * 4 - 0xc0;
+ addr = (frame1->prev->bottom
+ + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
+ + FRAME_SAVED_I0);
+ else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8)
+ addr = (frame1->prev->bottom
+ + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE
+ + FRAME_SAVED_L0);
+ else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8)
+ addr = frame1->frame + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE
+ - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE);
+#ifdef FP0_REGNUM
else if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32)
- addr = frame1->frame + (regnum - FP0_REGNUM) * 4 - 0x80;
+ addr = frame1->frame + (regnum - FP0_REGNUM) * 4
+ - (FP_REGISTER_BYTES);
+#ifdef GDB_TARGET_IS_SPARC64
+ else if (regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM)
+ addr = frame1->frame + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8
+ - (FP_REGISTER_BYTES);
+#endif
+#endif /* FP0_REGNUM */
else if (regnum >= Y_REGNUM && regnum < NUM_REGS)
- addr = frame1->frame + (regnum - Y_REGNUM) * 4 - 0xe0;
+ addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE
+ - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE);
}
else if (frame1->flat)
{
/* Normal frame. Local and In registers are saved on stack. */
if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8)
addr = (frame1->prev->bottom
- + (regnum - I0_REGNUM) * REGISTER_RAW_SIZE (I0_REGNUM)
+ + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
+ FRAME_SAVED_I0);
else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8)
addr = (frame1->prev->bottom
- + (regnum - L0_REGNUM) * REGISTER_RAW_SIZE (L0_REGNUM)
+ + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE
+ FRAME_SAVED_L0);
else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8)
{
/* Definitely see tm-sparc.h for more doc of the frame format here. */
+#ifdef GDB_TARGET_IS_SPARC64
+#define DUMMY_REG_SAVE_OFFSET (128 + 16)
+#else
+#define DUMMY_REG_SAVE_OFFSET 0x60
+#endif
+
+/* See tm-sparc.h for how this is calculated. */
+#ifdef FP0_REGNUM
+#define DUMMY_STACK_REG_BUF_SIZE \
+(((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
+#else
+#define DUMMY_STACK_REG_BUF_SIZE \
+(((8+8+8) * SPARC_INTREG_SIZE) )
+#endif /* FP0_REGNUM */
+#define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
+
void
sparc_push_dummy_frame ()
{
CORE_ADDR sp, old_sp;
- char register_temp[0x140];
-
- old_sp = sp = read_register (SP_REGNUM);
-
+ char register_temp[DUMMY_STACK_SIZE];
+
+ old_sp = sp = read_sp ();
+
+#ifdef GDB_TARGET_IS_SPARC64
+ /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
+ read_register_bytes (REGISTER_BYTE (PC_REGNUM), ®ister_temp[0],
+ REGISTER_RAW_SIZE (PC_REGNUM) * 7);
+ read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), ®ister_temp[8],
+ REGISTER_RAW_SIZE (PSTATE_REGNUM));
+ /* FIXME: not sure what needs to be saved here. */
+#else
/* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0],
REGISTER_RAW_SIZE (Y_REGNUM) * 8);
+#endif
- read_register_bytes (REGISTER_BYTE (O0_REGNUM), ®ister_temp[8 * 4],
- REGISTER_RAW_SIZE (O0_REGNUM) * 8);
+ read_register_bytes (REGISTER_BYTE (O0_REGNUM),
+ ®ister_temp[8 * SPARC_INTREG_SIZE],
+ SPARC_INTREG_SIZE * 8);
- read_register_bytes (REGISTER_BYTE (G0_REGNUM), ®ister_temp[16 * 4],
- REGISTER_RAW_SIZE (G0_REGNUM) * 8);
+ read_register_bytes (REGISTER_BYTE (G0_REGNUM),
+ ®ister_temp[16 * SPARC_INTREG_SIZE],
+ SPARC_INTREG_SIZE * 8);
- read_register_bytes (REGISTER_BYTE (FP0_REGNUM), ®ister_temp[24 * 4],
- REGISTER_RAW_SIZE (FP0_REGNUM) * 32);
+#ifdef FP0_REGNUM
+ read_register_bytes (REGISTER_BYTE (FP0_REGNUM),
+ ®ister_temp[24 * SPARC_INTREG_SIZE],
+ FP_REGISTER_BYTES);
+#endif /* FP0_REGNUM */
- sp -= 0x140;
+ sp -= DUMMY_STACK_SIZE;
- write_register (SP_REGNUM, sp);
+ write_sp (sp);
- write_memory (sp + 0x60, ®ister_temp[0], (8 + 8 + 8 + 32) * 4);
+ write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0],
+ DUMMY_STACK_REG_BUF_SIZE);
- write_register (FP_REGNUM, old_sp);
+ if (strcmp (target_shortname, "sim") != 0)
+ {
+ write_fp (old_sp);
- /* Set return address register for the call dummy to the current PC. */
- write_register (I7_REGNUM, read_pc() - 8);
+ /* Set return address register for the call dummy to the current PC. */
+ write_register (I7_REGNUM, read_pc() - 8);
+ }
+ else
+ {
+ /* The call dummy will write this value to FP before executing
+ the 'save'. This ensures that register window flushes work
+ correctly in the simulator. */
+ write_register (G0_REGNUM+1, read_register (FP_REGNUM));
+
+ /* The call dummy will write this value to FP after executing
+ the 'save'. */
+ write_register (G0_REGNUM+2, old_sp);
+
+ /* The call dummy will write this value to the return address (%i7) after
+ executing the 'save'. */
+ write_register (G0_REGNUM+3, read_pc() - 8);
+
+ /* Set the FP that the call dummy will be using after the 'save'.
+ This makes backtraces from an inferior function call work properly. */
+ write_register (FP_REGNUM, old_sp);
+ }
}
/* sparc_frame_find_saved_regs (). This function is here only because
is a return address minus 8.) sparc_pop_frame knows how to
deal with that. Other routines might or might not.
- See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information
+ See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
about how this works. */
static void sparc_frame_find_saved_regs PARAMS ((struct frame_info *,
memset (saved_regs_addr, 0, sizeof (*saved_regs_addr));
if (fi->pc >= (fi->bottom ? fi->bottom :
- read_register (SP_REGNUM))
+ read_sp ())
&& fi->pc <= FRAME_FP(fi))
{
/* Dummy frame. All but the window regs are in there somewhere. */
for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++)
saved_regs_addr->regs[regnum] =
- frame_addr + (regnum - G0_REGNUM) * 4 - 0xa0;
+ frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE
+ - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE;
for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++)
saved_regs_addr->regs[regnum] =
- frame_addr + (regnum - I0_REGNUM) * 4 - 0xc0;
+ frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
+ - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE;
+#ifdef FP0_REGNUM
for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++)
saved_regs_addr->regs[regnum] =
- frame_addr + (regnum - FP0_REGNUM) * 4 - 0x80;
+ frame_addr + (regnum - FP0_REGNUM) * 4
+ - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE;
+#ifdef GDB_TARGET_IS_SPARC64
+ for (regnum = FP0_REGNUM + 32; regnum < FP_MAX_REGNUM; regnum++)
+ saved_regs_addr->regs[regnum] =
+ frame_addr + 32 * 4 + (regnum - FP0_REGNUM - 32) * 4
+ - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE;
+#endif
+#endif /* FP0_REGNUM */
+#ifdef GDB_TARGET_IS_SPARC64
+ for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++)
+ {
+ saved_regs_addr->regs[regnum] =
+ frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE
+ - DUMMY_STACK_REG_BUF_SIZE;
+ }
+ saved_regs_addr->regs[PSTATE_REGNUM] =
+ frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE;
+#else
for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++)
saved_regs_addr->regs[regnum] =
- frame_addr + (regnum - Y_REGNUM) * 4 - 0xe0;
+ frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE
+ - DUMMY_STACK_REG_BUF_SIZE;
+#endif
frame_addr = fi->bottom ?
- fi->bottom : read_register (SP_REGNUM);
+ fi->bottom : read_sp ();
}
else if (fi->flat)
{
{
/* Normal frame. Just Local and In registers */
frame_addr = fi->bottom ?
- fi->bottom : read_register (SP_REGNUM);
+ fi->bottom : read_sp ();
for (regnum = L0_REGNUM; regnum < L0_REGNUM+8; regnum++)
saved_regs_addr->regs[regnum] =
- (frame_addr + (regnum - L0_REGNUM) * REGISTER_RAW_SIZE (L0_REGNUM)
+ (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE
+ FRAME_SAVED_L0);
for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++)
saved_regs_addr->regs[regnum] =
- (frame_addr + (regnum - I0_REGNUM) * REGISTER_RAW_SIZE (I0_REGNUM)
+ (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
+ FRAME_SAVED_I0);
}
if (fi->next)
CORE_ADDR next_next_frame_addr =
(fi->next->bottom ?
fi->next->bottom :
- read_register (SP_REGNUM));
+ read_sp ());
for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++)
saved_regs_addr->regs[regnum] =
(next_next_frame_addr
- + (regnum - O0_REGNUM) * REGISTER_RAW_SIZE (O0_REGNUM)
+ + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE
+ FRAME_SAVED_I0);
}
}
/* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
+ /* FIXME -- should this adjust for the sparc64 offset? */
saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi);
}
int regnum;
sparc_frame_find_saved_regs (frame, &fsr);
+#ifdef FP0_REGNUM
if (fsr.regs[FP0_REGNUM])
{
- read_memory (fsr.regs[FP0_REGNUM], raw_buffer, 32 * 4);
- write_register_bytes (REGISTER_BYTE (FP0_REGNUM), raw_buffer, 32 * 4);
+ read_memory (fsr.regs[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES);
+ write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
+ raw_buffer, FP_REGISTER_BYTES);
}
+#ifndef GDB_TARGET_IS_SPARC64
if (fsr.regs[FPS_REGNUM])
{
read_memory (fsr.regs[FPS_REGNUM], raw_buffer, 4);
read_memory (fsr.regs[CPS_REGNUM], raw_buffer, 4);
write_register_bytes (REGISTER_BYTE (CPS_REGNUM), raw_buffer, 4);
}
+#endif
+#endif /* FP0_REGNUM */
if (fsr.regs[G1_REGNUM])
{
- read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * 4);
- write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 7 * 4);
+ read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE);
+ write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer,
+ 7 * SPARC_INTREG_SIZE);
}
if (frame->flat)
individually. */
for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum)
if (fsr.regs[regnum])
- write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
+ write_register (regnum, read_memory_integer (fsr.regs[regnum],
+ SPARC_INTREG_SIZE));
for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum)
if (fsr.regs[regnum])
- write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
+ write_register (regnum, read_memory_integer (fsr.regs[regnum],
+ SPARC_INTREG_SIZE));
/* Handle all outs except stack pointer (o0-o5; o7). */
for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum)
if (fsr.regs[regnum])
- write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
+ write_register (regnum, read_memory_integer (fsr.regs[regnum],
+ SPARC_INTREG_SIZE));
if (fsr.regs[O0_REGNUM + 7])
write_register (O0_REGNUM + 7,
- read_memory_integer (fsr.regs[O0_REGNUM + 7], 4));
+ read_memory_integer (fsr.regs[O0_REGNUM + 7],
+ SPARC_INTREG_SIZE));
- write_register (SP_REGNUM, frame->frame, 4);
+ write_sp (frame->frame);
}
else if (fsr.regs[I0_REGNUM])
{
char reg_temp[REGISTER_BYTES];
- read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * 4);
+ read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE);
/* Get the ins and locals which we are about to restore. Just
moving the stack pointer is all that is really needed, except
locals from the registers array, so we need to muck with the
registers array. */
sp = fsr.regs[SP_REGNUM];
- read_memory (sp, reg_temp, REGISTER_RAW_SIZE (L0_REGNUM) * 16);
+#ifdef GDB_TARGET_IS_SPARC64
+ if (sp & 1)
+ sp += 2047;
+#endif
+ read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16);
/* Restore the out registers.
Among other things this writes the new stack pointer. */
write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer,
- REGISTER_RAW_SIZE (O0_REGNUM) * 8);
+ SPARC_INTREG_SIZE * 8);
write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp,
- REGISTER_RAW_SIZE (L0_REGNUM) * 16);
+ SPARC_INTREG_SIZE * 16);
}
+#ifndef GDB_TARGET_IS_SPARC64
if (fsr.regs[PS_REGNUM])
write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4));
+#endif
if (fsr.regs[Y_REGNUM])
- write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], 4));
+ write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], REGISTER_RAW_SIZE (Y_REGNUM)));
if (fsr.regs[PC_REGNUM])
{
/* Explicitly specified PC (and maybe NPC) -- just restore them. */
- write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 4));
+ write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM],
+ REGISTER_RAW_SIZE (PC_REGNUM)));
if (fsr.regs[NPC_REGNUM])
write_register (NPC_REGNUM,
- read_memory_integer (fsr.regs[NPC_REGNUM], 4));
+ read_memory_integer (fsr.regs[NPC_REGNUM],
+ REGISTER_RAW_SIZE (NPC_REGNUM)));
}
else if (frame->flat)
{
if (frame->pc_addr)
- pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (frame->pc_addr, 4));
+ pc = PC_ADJUST ((CORE_ADDR)
+ read_memory_integer (frame->pc_addr,
+ REGISTER_RAW_SIZE (PC_REGNUM)));
else
{
/* I think this happens only in the innermost frame, if so then
else if (fsr.regs[I7_REGNUM])
{
/* Return address in %i7 -- adjust it, then restore PC and NPC from it */
- pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM], 4));
+ pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM],
+ SPARC_INTREG_SIZE));
write_register (PC_REGNUM, pc);
write_register (NPC_REGNUM, pc + 4);
}
char buf[4];
int err;
- err = target_read_memory (pc + 8, buf, sizeof(long));
+ err = target_read_memory (pc + 8, buf, 4);
insn = extract_unsigned_integer (buf, 4);
- if ((err == 0) && (insn & 0xfffffe00) == 0)
+ if ((err == 0) && (insn & 0xffc00000) == 0)
return pc+12;
else
return pc+8;
*/
-/* Given a pointer to a general register set in /proc format (gregset_t *),
- unpack the register contents and supply them as gdb's idea of the current
- register values. */
+/* Given a pointer to a general register set in /proc format (gregset_t *),
+ unpack the register contents and supply them as gdb's idea of the current
+ register values. */
void
supply_gregset (gregsetp)
{
register int regi;
register prgreg_t *regp = (prgreg_t *) gregsetp;
+ static char zerobuf[MAX_REGISTER_RAW_SIZE] = {0};
/* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
for (regi = G0_REGNUM ; regi <= I7_REGNUM ; regi++)
supply_register (PC_REGNUM, (char *) (regp + R_PC));
supply_register (NPC_REGNUM,(char *) (regp + R_nPC));
supply_register (Y_REGNUM, (char *) (regp + R_Y));
+
+ /* Fill inaccessible registers with zero. */
+ supply_register (WIM_REGNUM, zerobuf);
+ supply_register (TBR_REGNUM, zerobuf);
+ supply_register (CPS_REGNUM, zerobuf);
}
void
{
int regi;
register prgreg_t *regp = (prgreg_t *) gregsetp;
- extern char registers[];
for (regi = 0 ; regi <= R_I7 ; regi++)
{
register int regi;
char *from;
- for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++)
+ for (regi = FP0_REGNUM ; regi < FP_MAX_REGNUM ; regi++)
{
from = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM];
supply_register (regi, from);
(fpregset_t *), update the register specified by REGNO from gdb's idea
of the current floating point register set. If REGNO is -1, update
them all. */
+/* ??? This will probably need some changes for sparc64. */
void
fill_fpregset (fpregsetp, regno)
int regi;
char *to;
char *from;
- extern char registers[];
- for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++)
+ for (regi = FP0_REGNUM ; regi < FP_MAX_REGNUM ; regi++)
{
if ((regno == -1) || (regno == regi))
{
return 1;
}
#endif /* GET_LONGJMP_TARGET */
+\f
+#ifdef STATIC_TRANSFORM_NAME
+/* SunPRO (3.0 at least), encodes the static variables. This is not
+ related to C++ mangling, it is done for C too. */
+
+char *
+sunpro_static_transform_name (name)
+ char *name;
+{
+ char *p;
+ if (name[0] == '$')
+ {
+ /* For file-local statics there will be a dollar sign, a bunch
+ of junk (the contents of which match a string given in the
+ N_OPT), a period and the name. For function-local statics
+ there will be a bunch of junk (which seems to change the
+ second character from 'A' to 'B'), a period, the name of the
+ function, and the name. So just skip everything before the
+ last period. */
+ p = strrchr (name, '.');
+ if (p != NULL)
+ name = p + 1;
+ }
+ return name;
+}
+#endif /* STATIC_TRANSFORM_NAME */
+\f
+
+/* Utilities for printing registers.
+ Page numbers refer to the SPARC Architecture Manual. */
+
+static void dump_ccreg PARAMS ((char *, int));
+
+static void
+dump_ccreg (reg, val)
+ char *reg;
+ int val;
+{
+ /* page 41 */
+ printf_unfiltered ("%s:%s,%s,%s,%s", reg,
+ val & 8 ? "N" : "NN",
+ val & 4 ? "Z" : "NZ",
+ val & 2 ? "O" : "NO",
+ val & 1 ? "C" : "NC"
+ );
+}
+
+static char *
+decode_asi (val)
+ int val;
+{
+ /* page 72 */
+ switch (val)
+ {
+ case 4 : return "ASI_NUCLEUS";
+ case 0x0c : return "ASI_NUCLEUS_LITTLE";
+ case 0x10 : return "ASI_AS_IF_USER_PRIMARY";
+ case 0x11 : return "ASI_AS_IF_USER_SECONDARY";
+ case 0x18 : return "ASI_AS_IF_USER_PRIMARY_LITTLE";
+ case 0x19 : return "ASI_AS_IF_USER_SECONDARY_LITTLE";
+ case 0x80 : return "ASI_PRIMARY";
+ case 0x81 : return "ASI_SECONDARY";
+ case 0x82 : return "ASI_PRIMARY_NOFAULT";
+ case 0x83 : return "ASI_SECONDARY_NOFAULT";
+ case 0x88 : return "ASI_PRIMARY_LITTLE";
+ case 0x89 : return "ASI_SECONDARY_LITTLE";
+ case 0x8a : return "ASI_PRIMARY_NOFAULT_LITTLE";
+ case 0x8b : return "ASI_SECONDARY_NOFAULT_LITTLE";
+ default : return NULL;
+ }
+}
+
+/* PRINT_REGISTER_HOOK routine.
+ Pretty print various registers. */
+/* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
+
+void
+sparc_print_register_hook (regno)
+ int regno;
+{
+ ULONGEST val;
+
+ /* Handle double/quad versions of lower 32 fp regs. */
+ if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32
+ && (regno & 1) == 0)
+ {
+ char value[16];
+
+ if (!read_relative_register_raw_bytes (regno, value)
+ && !read_relative_register_raw_bytes (regno + 1, value + 4))
+ {
+ printf_unfiltered ("\t");
+ print_floating (value, builtin_type_double, gdb_stdout);
+ }
+#if 0 /* FIXME: gdb doesn't handle long doubles */
+ if ((regno & 3) == 0)
+ {
+ if (!read_relative_register_raw_bytes (regno + 2, value + 8)
+ && !read_relative_register_raw_bytes (regno + 3, value + 12))
+ {
+ printf_unfiltered ("\t");
+ print_floating (value, builtin_type_long_double, gdb_stdout);
+ }
+ }
+#endif
+ return;
+ }
+
+#if 0 /* FIXME: gdb doesn't handle long doubles */
+ /* Print upper fp regs as long double if appropriate. */
+ if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM
+ /* We test for even numbered regs and not a multiple of 4 because
+ the upper fp regs are recorded as doubles. */
+ && (regno & 1) == 0)
+ {
+ char value[16];
+
+ if (!read_relative_register_raw_bytes (regno, value)
+ && !read_relative_register_raw_bytes (regno + 1, value + 8))
+ {
+ printf_unfiltered ("\t");
+ print_floating (value, builtin_type_long_double, gdb_stdout);
+ }
+ return;
+ }
+#endif
+
+ /* FIXME: Some of these are priviledged registers.
+ Not sure how they should be handled. */
+
+#define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
+
+ val = read_register (regno);
+
+ /* pages 40 - 60 */
+ switch (regno)
+ {
+#ifdef GDB_TARGET_IS_SPARC64
+ case CCR_REGNUM :
+ printf_unfiltered("\t");
+ dump_ccreg ("xcc", val >> 4);
+ printf_unfiltered(", ");
+ dump_ccreg ("icc", val & 15);
+ break;
+ case FPRS_REGNUM :
+ printf ("\tfef:%d, du:%d, dl:%d",
+ BITS (2, 1), BITS (1, 1), BITS (0, 1));
+ break;
+ case FSR_REGNUM :
+ {
+ static char *fcc[4] = { "=", "<", ">", "?" };
+ static char *rd[4] = { "N", "0", "+", "-" };
+ /* Long, yes, but I'd rather leave it as is and use a wide screen. */
+ printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
+ fcc[BITS (10, 3)], fcc[BITS (32, 3)],
+ fcc[BITS (34, 3)], fcc[BITS (36, 3)],
+ rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
+ BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31));
+ break;
+ }
+ case ASI_REGNUM :
+ {
+ char *asi = decode_asi (val);
+ if (asi != NULL)
+ printf ("\t%s", asi);
+ break;
+ }
+ case VER_REGNUM :
+ printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
+ BITS (48, 0xffff), BITS (32, 0xffff),
+ BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
+ break;
+ case PSTATE_REGNUM :
+ {
+ static char *mm[4] = { "tso", "pso", "rso", "?" };
+ printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
+ BITS (9, 1), BITS (8, 1), mm[BITS (6, 3)], BITS (5, 1),
+ BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1),
+ BITS (0, 1));
+ break;
+ }
+ case TSTATE_REGNUM :
+ /* FIXME: print all 4? */
+ break;
+ case TT_REGNUM :
+ /* FIXME: print all 4? */
+ break;
+ case TPC_REGNUM :
+ /* FIXME: print all 4? */
+ break;
+ case TNPC_REGNUM :
+ /* FIXME: print all 4? */
+ break;
+ case WSTATE_REGNUM :
+ printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
+ break;
+ case CWP_REGNUM :
+ printf ("\t%d", BITS (0, 31));
+ break;
+ case CANSAVE_REGNUM :
+ printf ("\t%-2d before spill", BITS (0, 31));
+ break;
+ case CANRESTORE_REGNUM :
+ printf ("\t%-2d before fill", BITS (0, 31));
+ break;
+ case CLEANWIN_REGNUM :
+ printf ("\t%-2d before clean", BITS (0, 31));
+ break;
+ case OTHERWIN_REGNUM :
+ printf ("\t%d", BITS (0, 31));
+ break;
+#else
+ case PS_REGNUM:
+ printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
+ BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
+ BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
+ BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
+ BITS (0, 31));
+ break;
+ case FPS_REGNUM:
+ {
+ static char *fcc[4] = { "=", "<", ">", "?" };
+ static char *rd[4] = { "N", "0", "+", "-" };
+ /* Long, yes, but I'd rather leave it as is and use a wide screen. */
+ printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
+ "fcc:%s, aexc:%d, cexc:%d",
+ rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
+ BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31),
+ BITS (0, 31));
+ break;
+ }
+
+#endif /* GDB_TARGET_IS_SPARC64 */
+ }
+
+#undef BITS
+}
+\f
+int
+gdb_print_insn_sparc (memaddr, info)
+ bfd_vma memaddr;
+ disassemble_info *info;
+{
+ /* It's necessary to override mach again because print_insn messes it up. */
+ info->mach = TM_PRINT_INSN_MACH;
+ return print_insn_sparc (memaddr, info);
+}
+\f
+/* The SPARC passes the arguments on the stack; arguments smaller
+ than an int are promoted to an int. */
+
+CORE_ADDR
+sparc_push_arguments (nargs, args, sp, struct_return, struct_addr)
+ int nargs;
+ value_ptr *args;
+ CORE_ADDR sp;
+ int struct_return;
+ CORE_ADDR struct_addr;
+{
+ int i;
+ int accumulate_size = 0;
+ struct sparc_arg
+ {
+ char *contents;
+ int len;
+ int offset;
+ };
+ struct sparc_arg *sparc_args =
+ (struct sparc_arg*)alloca (nargs * sizeof (struct sparc_arg));
+ struct sparc_arg *m_arg;
+
+ /* Promote arguments if necessary, and calculate their stack offsets
+ and sizes. */
+ for (i = 0, m_arg = sparc_args; i < nargs; i++, m_arg++)
+ {
+ value_ptr arg = args[i];
+ struct type *arg_type = check_typedef (VALUE_TYPE (arg));
+ /* Cast argument to long if necessary as the compiler does it too. */
+ switch (TYPE_CODE (arg_type))
+ {
+ case TYPE_CODE_INT:
+ case TYPE_CODE_BOOL:
+ case TYPE_CODE_CHAR:
+ case TYPE_CODE_RANGE:
+ case TYPE_CODE_ENUM:
+ if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
+ {
+ arg_type = builtin_type_long;
+ arg = value_cast (arg_type, arg);
+ }
+ break;
+ default:
+ break;
+ }
+ m_arg->len = TYPE_LENGTH (arg_type);
+ m_arg->offset = accumulate_size;
+ accumulate_size = (accumulate_size + m_arg->len + 3) & ~3;
+ m_arg->contents = VALUE_CONTENTS(arg);
+ }
+
+ /* Make room for the arguments on the stack. */
+ accumulate_size += CALL_DUMMY_STACK_ADJUST;
+ sp = ((sp - accumulate_size) & ~7) + CALL_DUMMY_STACK_ADJUST;
+
+ /* `Push' arguments on the stack. */
+ for (i = nargs; m_arg--, --i >= 0; )
+ write_memory(sp + m_arg->offset, m_arg->contents, m_arg->len);
+
+ return sp;
+}
+
+
+/* Extract from an array REGBUF containing the (raw) register state
+ a function return value of type TYPE, and copy that, in virtual format,
+ into VALBUF. */
+
+void
+sparc_extract_return_value (type, regbuf, valbuf)
+ struct type *type;
+ char *regbuf;
+ char *valbuf;
+{
+ int typelen = TYPE_LENGTH (type);
+ int regsize = REGISTER_RAW_SIZE (O0_REGNUM);
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU)
+ memcpy (valbuf, ®buf [REGISTER_BYTE (FP0_REGNUM)], typelen);
+ else
+ memcpy (valbuf,
+ ®buf [O0_REGNUM * regsize +
+ (typelen >= regsize ? 0 : regsize - typelen)],
+ typelen);
+}
+
+
+/* Write into appropriate registers a function return value
+ of type TYPE, given in virtual format. On SPARCs with FPUs,
+ float values are returned in %f0 (and %f1). In all other cases,
+ values are returned in register %o0. */
+
+void
+sparc_store_return_value (type, valbuf)
+ struct type *type;
+ char *valbuf;
+{
+ int regno;
+ char buffer[MAX_REGISTER_RAW_SIZE];
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU)
+ /* Floating-point values are returned in the register pair */
+ /* formed by %f0 and %f1 (doubles are, anyway). */
+ regno = FP0_REGNUM;
+ else
+ /* Other values are returned in register %o0. */
+ regno = O0_REGNUM;
+
+ /* Add leading zeros to the value. */
+ if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE(regno))
+ {
+ bzero (buffer, REGISTER_RAW_SIZE(regno));
+ memcpy (buffer + REGISTER_RAW_SIZE(regno) - TYPE_LENGTH (type), valbuf,
+ TYPE_LENGTH (type));
+ write_register_bytes (REGISTER_BYTE (regno), buffer,
+ REGISTER_RAW_SIZE(regno));
+ }
+ else
+ write_register_bytes (REGISTER_BYTE (regno), valbuf, TYPE_LENGTH (type));
+}
+
+
+/* Insert the function address into a call dummy instsruction sequence
+ stored at DUMMY.
+
+ For structs and unions, if the function was compiled with Sun cc,
+ it expects 'unimp' after the call. But gcc doesn't use that
+ (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
+ can assume it is operating on a pristine CALL_DUMMY, not one that
+ has already been customized for a different function). */
+
+void
+sparc_fix_call_dummy (dummy, pc, fun, value_type, using_gcc)
+ char *dummy;
+ CORE_ADDR pc;
+ CORE_ADDR fun;
+ struct type *value_type;
+ int using_gcc;
+{
+ int i;
+
+ /* Store the relative adddress of the target function into the
+ 'call' instruction. */
+ store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4,
+ (0x40000000
+ | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2)
+ & 0x3fffffff)));
+
+ /* Comply with strange Sun cc calling convention for struct-returning
+ functions. */
+ if (!using_gcc
+ && (TYPE_CODE (value_type) == TYPE_CODE_STRUCT
+ || TYPE_CODE (value_type) == TYPE_CODE_UNION))
+ store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4,
+ TYPE_LENGTH (value_type) & 0x1fff);
+
+#ifndef GDB_TARGET_IS_SPARC64
+ /* If this is not a simulator target, change the first four instructions
+ of the call dummy to NOPs. Those instructions include a 'save'
+ instruction and are designed to work around problems with register
+ window flushing in the simulator. */
+ if (strcmp (target_shortname, "sim") != 0)
+ {
+ for (i = 0; i < 4; i++)
+ store_unsigned_integer (dummy + (i * 4), 4, 0x01000000);
+ }
+#endif
+}
+
+
+/* Set target byte order based on machine type. */
+
+static int
+sparc_target_architecture_hook (ap)
+ const bfd_arch_info_type *ap;
+{
+ int i, j;
+
+#ifdef TARGET_BYTE_ORDER_SELECTABLE
+ if (ap->mach == bfd_mach_sparc_sparclite_le)
+ target_byte_order = LITTLE_ENDIAN;
+#endif
+ return 1;
+}
+
+\f
+void
+_initialize_sparc_tdep ()
+{
+ tm_print_insn = gdb_print_insn_sparc;
+ tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */
+ target_architecture_hook = sparc_target_architecture_hook;
+}
+
+
+#ifdef GDB_TARGET_IS_SPARC64
+
+/* Compensate for stack bias. Note that we currently don't handle mixed
+ 32/64 bit code. */
+CORE_ADDR
+sparc64_read_sp ()
+{
+ CORE_ADDR sp = read_register (SP_REGNUM);
+
+ if (sp & 1)
+ sp += 2047;
+ return sp;
+}
+
+CORE_ADDR
+sparc64_read_fp ()
+{
+ CORE_ADDR fp = read_register (FP_REGNUM);
+
+ if (fp & 1)
+ fp += 2047;
+ return fp;
+}
+
+void
+sparc64_write_sp (val)
+ CORE_ADDR val;
+{
+ CORE_ADDR oldsp = read_register (SP_REGNUM);
+ if (oldsp & 1)
+ write_register (SP_REGNUM, val - 2047);
+ else
+ write_register (SP_REGNUM, val);
+}
+
+void
+sparc64_write_fp (val)
+ CORE_ADDR val;
+{
+ CORE_ADDR oldfp = read_register (FP_REGNUM);
+ if (oldfp & 1)
+ write_register (FP_REGNUM, val - 2047);
+ else
+ write_register (FP_REGNUM, val);
+}
+
+/* The SPARC 64 ABI passes floating-point arguments in FP0-31. They are
+ also copied onto the stack in the correct places. */
+
+CORE_ADDR
+sp64_push_arguments (nargs, args, sp, struct_return, struct_retaddr)
+ int nargs;
+ value_ptr *args;
+ CORE_ADDR sp;
+ unsigned char struct_return;
+ CORE_ADDR struct_retaddr;
+{
+ int x;
+ int regnum = 0;
+ CORE_ADDR tempsp;
+
+ sp = (sp & ~(((unsigned long)TYPE_LENGTH (builtin_type_long)) - 1UL));
+
+ /* Figure out how much space we'll need. */
+ for (x = nargs - 1; x >= 0; x--)
+ {
+ int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x])));
+ value_ptr copyarg = args[x];
+ int copylen = len;
+
+ /* This code is, of course, no longer correct. */
+ if (copylen < TYPE_LENGTH (builtin_type_long))
+ {
+ copyarg = value_cast(builtin_type_long, copyarg);
+ copylen = TYPE_LENGTH (builtin_type_long);
+ }
+ sp -= copylen;
+ }
+
+ /* Round down. */
+ sp = sp & ~7;
+ tempsp = sp;
+
+ /* Now write the arguments onto the stack, while writing FP arguments
+ into the FP registers. */
+ for (x = 0; x < nargs; x++)
+ {
+ int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x])));
+ value_ptr copyarg = args[x];
+ int copylen = len;
+
+ /* This code is, of course, no longer correct. */
+ if (copylen < TYPE_LENGTH (builtin_type_long))
+ {
+ copyarg = value_cast(builtin_type_long, copyarg);
+ copylen = TYPE_LENGTH (builtin_type_long);
+ }
+ write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen);
+ tempsp += copylen;
+ if (TYPE_CODE (VALUE_TYPE (args[x])) == TYPE_CODE_FLT && regnum < 32)
+ {
+ /* This gets copied into a FP register. */
+ int nextreg = regnum + 2;
+ char *data = VALUE_CONTENTS (args[x]);
+ /* Floats go into the lower half of a FP register pair; quads
+ use 2 pairs. */
+
+ if (len == 16)
+ nextreg += 2;
+ else if (len == 4)
+ regnum++;
+
+ write_register_bytes (REGISTER_BYTE (FP0_REGNUM + regnum),
+ data,
+ len);
+ regnum = nextreg;
+ }
+ }
+ return sp;
+}
+
+/* Values <= 32 bytes are returned in o0-o3 (floating-point values are
+ returned in f0-f3). */
+void
+sparc64_extract_return_value (type, regbuf, valbuf, bitoffset)
+ struct type *type;
+ char *regbuf;
+ char *valbuf;
+ int bitoffset;
+{
+ int typelen = TYPE_LENGTH (type);
+ int regsize = REGISTER_RAW_SIZE (O0_REGNUM);
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU)
+ {
+ memcpy (valbuf, ®buf [REGISTER_BYTE (FP0_REGNUM)], typelen);
+ return;
+ }
+
+ if (TYPE_CODE (type) != TYPE_CODE_STRUCT
+ || (TYPE_LENGTH (type) > 32))
+ {
+ memcpy (valbuf,
+ ®buf [O0_REGNUM * regsize +
+ (typelen >= regsize ? 0 : regsize - typelen)],
+ typelen);
+ return;
+ }
+ else
+ {
+ char *o0 = ®buf[O0_REGNUM * regsize];
+ char *f0 = ®buf[FP0_REGNUM * regsize];
+ int x;
+
+ for (x = 0; x < TYPE_NFIELDS (type); x++)
+ {
+ struct field *f = &TYPE_FIELDS(type)[x];
+ /* FIXME: We may need to handle static fields here. */
+ int whichreg = (f->loc.bitpos + bitoffset) / 32;
+ int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8;
+ int where = (f->loc.bitpos + bitoffset) / 8;
+ int size = TYPE_LENGTH (f->type);
+ int typecode = TYPE_CODE (f->type);
+
+ if (typecode == TYPE_CODE_STRUCT)
+ {
+ sparc64_extract_return_value (f->type,
+ regbuf,
+ valbuf,
+ bitoffset + f->loc.bitpos);
+ }
+ else if (typecode == TYPE_CODE_FLT)
+ {
+ memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size);
+ }
+ else
+ {
+ memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size);
+ }
+ }
+ }
+}
+#endif