/* Target-dependent code for SPARC.
- Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
- Free Software Foundation, Inc.
+ Copyright (C) 2003-2013 Free Software Foundation, Inc.
This file is part of GDB.
#include "value.h"
#include "gdb_assert.h"
-#include "gdb_string.h"
+#include <string.h>
#include "sparc-tdep.h"
+#include "sparc-ravenscar-thread.h"
struct regset;
/* Sign extension macros. */
#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
+#define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
#define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
/* Fetch the instruction at PC. Instructions are always big-endian
return ((insn & 0xc1c00000) == 0);
}
+/* Return non-zero if the instruction corresponding to PC is an
+ "annulled" branch, i.e. the annul bit is set. */
+
+int
+sparc_is_annulled_branch_insn (CORE_ADDR pc)
+{
+ /* The branch instructions featuring an annul bit can be identified
+ by the following bit patterns:
+
+ OP=0
+ OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
+ OP2=2: Branch on Integer Condition Codes (Bcc).
+ OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
+ OP2=6: Branch on FP Condition Codes (FBcc).
+ OP2=3 && Bit28=0:
+ Branch on Integer Register with Prediction (BPr).
+
+ This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
+ coprocessor branch instructions (Op2=7). */
+
+ const unsigned long insn = sparc_fetch_instruction (pc);
+ const unsigned op2 = X_OP2 (insn);
+
+ if ((X_OP (insn) == 0)
+ && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6)
+ || ((op2 == 3) && ((insn & 0x10000000) == 0))))
+ return X_A (insn);
+ else
+ return 0;
+}
+
/* OpenBSD/sparc includes StackGhost, which according to the author's
website http://stackghost.cerias.purdue.edu "... transparently and
automatically protects applications' stack frames; more
return 0;
}
+/* Check whether TYPE is "Complex Floating". */
+
+static int
+sparc_complex_floating_p (const struct type *type)
+{
+ switch (TYPE_CODE (type))
+ {
+ case TYPE_CODE_COMPLEX:
+ {
+ int len = TYPE_LENGTH (type);
+ return (len == 8 || len == 16 || len == 32);
+ }
+ default:
+ break;
+ }
+
+ return 0;
+}
+
/* Check whether TYPE is "Structure or Union".
In terms of Ada subprogram calls, arrays are treated the same as
int len = TYPE_LENGTH (type);
if (sparc_structure_or_union_p (type)
- || (sparc_floating_p (type) && len == 16))
+ || (sparc_floating_p (type) && len == 16)
+ || sparc_complex_floating_p (type))
{
/* Structure, Union and Quad-Precision Arguments. */
sp -= len;
sparc_alloc_frame_cache (void)
{
struct sparc_frame_cache *cache;
- int i;
cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
dynamic linker patches up the first PLT with some code that
starts with a SAVE instruction. Patch up PC such that it points
at the start of our PLT entry. */
- if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
+ if (tdep->plt_entry_size > 0 && in_plt_section (current_pc))
pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
insn = sparc_fetch_instruction (pc);
gdb_byte *valbuf)
{
int len = TYPE_LENGTH (type);
- gdb_byte buf[8];
+ gdb_byte buf[32];
gdb_assert (!sparc_structure_or_union_p (type));
gdb_assert (!(sparc_floating_p (type) && len == 16));
- if (sparc_floating_p (type))
+ if (sparc_floating_p (type) || sparc_complex_floating_p (type))
{
/* Floating return values. */
regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
if (len > 4)
regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
+ if (len > 8)
+ {
+ regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8);
+ regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12);
+ }
+ if (len > 16)
+ {
+ regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16);
+ regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20);
+ regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24);
+ regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28);
+ }
memcpy (valbuf, buf, len);
}
else
gdb_assert (!(sparc_floating_p (type) && len == 16));
gdb_assert (len <= 8);
- if (sparc_floating_p (type))
+ if (sparc_floating_p (type) || sparc_complex_floating_p (type))
{
/* Floating return values. */
memcpy (buf, valbuf, len);
regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
if (len > 4)
regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
+ if (len > 8)
+ {
+ regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8);
+ regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12);
+ }
+ if (len > 16)
+ {
+ regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16);
+ regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20);
+ regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24);
+ regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28);
+ }
}
else
{
}
static enum return_value_convention
-sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type,
+sparc32_return_value (struct gdbarch *gdbarch, struct value *function,
struct type *type, struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
if (sparc_structure_or_union_p (type)
|| (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
{
+ ULONGEST sp;
+ CORE_ADDR addr;
+
if (readbuf)
{
- ULONGEST sp;
- CORE_ADDR addr;
-
regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
read_memory (addr, readbuf, TYPE_LENGTH (type));
}
+ if (writebuf)
+ {
+ regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
+ addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
+ write_memory (addr, writebuf, TYPE_LENGTH (type));
+ }
return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
}
sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
{
return (sparc_structure_or_union_p (type)
- || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
+ || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)
+ || sparc_complex_floating_p (type));
}
static int
{
unsigned long insn = sparc_fetch_instruction (pc);
int conditional_p = X_COND (insn) & 0x7;
- int branch_p = 0;
+ int branch_p = 0, fused_p = 0;
long offset = 0; /* Must be signed for sign-extend. */
- if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
+ if (X_OP (insn) == 0 && X_OP2 (insn) == 3)
{
- /* Branch on Integer Register with Prediction (BPr). */
- branch_p = 1;
- conditional_p = 1;
+ if ((insn & 0x10000000) == 0)
+ {
+ /* Branch on Integer Register with Prediction (BPr). */
+ branch_p = 1;
+ conditional_p = 1;
+ }
+ else
+ {
+ /* Compare and Branch */
+ branch_p = 1;
+ fused_p = 1;
+ offset = 4 * X_DISP10 (insn);
+ }
}
else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
{
if (branch_p)
{
- if (conditional_p)
+ if (fused_p)
+ {
+ /* Fused compare-and-branch instructions are non-delayed,
+ and do not have an annuling capability. So we need to
+ always set a breakpoint on both the NPC and the branch
+ target address. */
+ gdb_assert (offset != 0);
+ return pc + offset;
+ }
+ else if (conditional_p)
{
/* For conditional branches, return nPC + 4 iff the annul
bit is 1. */
if (X_A (insn))
*npc = 0;
- gdb_assert (offset != 0);
return pc + offset;
}
}
set_gdbarch_regset_from_core_section (gdbarch,
sparc_regset_from_core_section);
+ register_sparc_ravenscar_ops (gdbarch);
+
return gdbarch;
}
\f
}
void
-sparc32_supply_fpregset (struct regcache *regcache,
+sparc32_supply_fpregset (const struct sparc_fpregset *fpregset,
+ struct regcache *regcache,
int regnum, const void *fpregs)
{
const gdb_byte *regs = fpregs;
for (i = 0; i < 32; i++)
{
if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
- regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
+ regcache_raw_supply (regcache, SPARC_F0_REGNUM + i,
+ regs + fpregset->r_f0_offset + (i * 4));
}
if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
- regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
+ regcache_raw_supply (regcache, SPARC32_FSR_REGNUM,
+ regs + fpregset->r_fsr_offset);
}
void
-sparc32_collect_fpregset (const struct regcache *regcache,
+sparc32_collect_fpregset (const struct sparc_fpregset *fpregset,
+ const struct regcache *regcache,
int regnum, void *fpregs)
{
gdb_byte *regs = fpregs;
for (i = 0; i < 32; i++)
{
if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
- regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
+ regcache_raw_collect (regcache, SPARC_F0_REGNUM + i,
+ regs + fpregset->r_f0_offset + (i * 4));
}
if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
- regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
+ regcache_raw_collect (regcache, SPARC32_FSR_REGNUM,
+ regs + fpregset->r_fsr_offset);
}
\f
4 * 4, /* %g1 */
-1 /* %l0 */
};
+
+const struct sparc_fpregset sparc32_sunos4_fpregset =
+{
+ 0 * 4, /* %f0 */
+ 33 * 4, /* %fsr */
+};
+
+const struct sparc_fpregset sparc32_bsd_fpregset =
+{
+ 0 * 4, /* %f0 */
+ 32 * 4, /* %fsr */
+};
\f
/* Provide a prototype to silence -Wmissing-prototypes. */
projects / deliverable / binutils-gdb.git / blobdiff