-/* Target-dependent code for the x86-64 for GDB, the GNU debugger.
+/* Target-dependent code for AMD64.
- Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by Jiri Smid, SuSE Labs.
This file is part of GDB.
#include "gdbcore.h"
#include "objfiles.h"
#include "regcache.h"
+#include "regset.h"
#include "symfile.h"
#include "gdb_assert.h"
#include "x86-64-tdep.h"
#include "i387-tdep.h"
-/* Register numbers of various important registers. */
+/* Note that the AMD64 architecture was previously known as x86-64.
+ The latter is (forever) engraved into the canonical system name as
+ returned by config.guess, and used as the name for the AMD64 port
+ of GNU/Linux. The BSD's have renamed their ports to amd64; they
+ don't like to shout. For GDB we prefer the amd64_-prefix over the
+ x86_64_-prefix since it's so much easier to type. */
-#define X86_64_RAX_REGNUM 0 /* %rax */
-#define X86_64_RDX_REGNUM 3 /* %rdx */
-#define X86_64_RDI_REGNUM 5 /* %rdi */
-#define X86_64_RBP_REGNUM 6 /* %rbp */
-#define X86_64_RSP_REGNUM 7 /* %rsp */
-#define X86_64_RIP_REGNUM 16 /* %rip */
-#define X86_64_EFLAGS_REGNUM 17 /* %eflags */
-#define X86_64_ST0_REGNUM 22 /* %st0 */
-#define X86_64_XMM0_REGNUM 38 /* %xmm0 */
-#define X86_64_XMM1_REGNUM 39 /* %xmm1 */
+/* Register information. */
-struct x86_64_register_info
+struct amd64_register_info
{
char *name;
struct type **type;
};
-static struct x86_64_register_info x86_64_register_info[] =
+static struct amd64_register_info amd64_register_info[] =
{
{ "rax", &builtin_type_int64 },
{ "rbx", &builtin_type_int64 },
{ "r15", &builtin_type_int64 },
{ "rip", &builtin_type_void_func_ptr },
{ "eflags", &builtin_type_int32 },
+ { "cs", &builtin_type_int32 },
+ { "ss", &builtin_type_int32 },
{ "ds", &builtin_type_int32 },
{ "es", &builtin_type_int32 },
{ "fs", &builtin_type_int32 },
{ "gs", &builtin_type_int32 },
- /* %st0 is register number 22. */
+ /* %st0 is register number 24. */
{ "st0", &builtin_type_i387_ext },
{ "st1", &builtin_type_i387_ext },
{ "st2", &builtin_type_i387_ext },
{ "fooff", &builtin_type_int32 },
{ "fop", &builtin_type_int32 },
- /* %xmm0 is register number 38. */
+ /* %xmm0 is register number 40. */
{ "xmm0", &builtin_type_v4sf },
{ "xmm1", &builtin_type_v4sf },
{ "xmm2", &builtin_type_v4sf },
};
/* Total number of registers. */
-#define X86_64_NUM_REGS \
- (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0]))
+#define AMD64_NUM_REGS \
+ (sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
/* Return the name of register REGNUM. */
static const char *
-x86_64_register_name (int regnum)
+amd64_register_name (int regnum)
{
- if (regnum >= 0 && regnum < X86_64_NUM_REGS)
- return x86_64_register_info[regnum].name;
+ if (regnum >= 0 && regnum < AMD64_NUM_REGS)
+ return amd64_register_info[regnum].name;
return NULL;
}
register REGNUM. */
static struct type *
-x86_64_register_type (struct gdbarch *gdbarch, int regnum)
+amd64_register_type (struct gdbarch *gdbarch, int regnum)
{
- gdb_assert (regnum >= 0 && regnum < X86_64_NUM_REGS);
+ gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS);
- return *x86_64_register_info[regnum].type;
+ return *amd64_register_info[regnum].type;
}
/* DWARF Register Number Mapping as defined in the System V psABI,
section 3.6. */
-static int x86_64_dwarf_regmap[] =
+static int amd64_dwarf_regmap[] =
{
/* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
- X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 3, 2,
- 4, X86_64_RDI_REGNUM,
+ AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
+ AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
+ AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
/* Frame Pointer Register RBP. */
- X86_64_RBP_REGNUM,
+ AMD64_RBP_REGNUM,
/* Stack Pointer Register RSP. */
- X86_64_RSP_REGNUM,
+ AMD64_RSP_REGNUM,
/* Extended Integer Registers 8 - 15. */
8, 9, 10, 11, 12, 13, 14, 15,
- /* Return Address RA. Not mapped. */
- -1,
+ /* Return Address RA. Mapped to RIP. */
+ AMD64_RIP_REGNUM,
/* SSE Registers 0 - 7. */
- X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
- X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
- X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
- X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
+ AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
+ AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
+ AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
+ AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
/* Extended SSE Registers 8 - 15. */
- X86_64_XMM0_REGNUM + 8, X86_64_XMM0_REGNUM + 9,
- X86_64_XMM0_REGNUM + 10, X86_64_XMM0_REGNUM + 11,
- X86_64_XMM0_REGNUM + 12, X86_64_XMM0_REGNUM + 13,
- X86_64_XMM0_REGNUM + 14, X86_64_XMM0_REGNUM + 15,
+ AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
+ AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
+ AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
+ AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
/* Floating Point Registers 0-7. */
- X86_64_ST0_REGNUM + 0, X86_64_ST0_REGNUM + 1,
- X86_64_ST0_REGNUM + 2, X86_64_ST0_REGNUM + 3,
- X86_64_ST0_REGNUM + 4, X86_64_ST0_REGNUM + 5,
- X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7
+ AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
+ AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
+ AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
+ AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7
};
-static const int x86_64_dwarf_regmap_len =
- (sizeof (x86_64_dwarf_regmap) / sizeof (x86_64_dwarf_regmap[0]));
+static const int amd64_dwarf_regmap_len =
+ (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
/* Convert DWARF register number REG to the appropriate register
number used by GDB. */
static int
-x86_64_dwarf_reg_to_regnum (int reg)
+amd64_dwarf_reg_to_regnum (int reg)
{
int regnum = -1;
- if (reg >= 0 || reg < x86_64_dwarf_regmap_len)
- regnum = x86_64_dwarf_regmap[reg];
+ if (reg >= 0 || reg < amd64_dwarf_regmap_len)
+ regnum = amd64_dwarf_regmap[reg];
if (regnum == -1)
warning ("Unmapped DWARF Register #%d encountered\n", reg);
return regnum;
}
-\f
-/* The returning of values is done according to the special algorithm.
- Some types are returned in registers an some (big structures) in
- memory. See the System V psABI for details. */
+/* Return nonzero if a value of type TYPE stored in register REGNUM
+ needs any special handling. */
+
+static int
+amd64_convert_register_p (int regnum, struct type *type)
+{
+ return i386_fp_regnum_p (regnum);
+}
+\f
-#define MAX_CLASSES 4
+/* Register classes as defined in the psABI. */
-enum x86_64_reg_class
+enum amd64_reg_class
{
- X86_64_NO_CLASS,
- X86_64_INTEGER_CLASS,
- X86_64_INTEGERSI_CLASS,
- X86_64_SSE_CLASS,
- X86_64_SSESF_CLASS,
- X86_64_SSEDF_CLASS,
- X86_64_SSEUP_CLASS,
- X86_64_X87_CLASS,
- X86_64_X87UP_CLASS,
- X86_64_MEMORY_CLASS
+ AMD64_INTEGER,
+ AMD64_SSE,
+ AMD64_SSEUP,
+ AMD64_X87,
+ AMD64_X87UP,
+ AMD64_COMPLEX_X87,
+ AMD64_NO_CLASS,
+ AMD64_MEMORY
};
-/* Return the union class of CLASS1 and CLASS2.
- See the System V psABI for details. */
+/* Return the union class of CLASS1 and CLASS2. See the psABI for
+ details. */
-static enum x86_64_reg_class
-merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
+static enum amd64_reg_class
+amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
{
/* Rule (a): If both classes are equal, this is the resulting class. */
if (class1 == class2)
/* Rule (b): If one of the classes is NO_CLASS, the resulting class
is the other class. */
- if (class1 == X86_64_NO_CLASS)
+ if (class1 == AMD64_NO_CLASS)
return class2;
- if (class2 == X86_64_NO_CLASS)
+ if (class2 == AMD64_NO_CLASS)
return class1;
/* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
- if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
- return X86_64_MEMORY_CLASS;
+ if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
+ return AMD64_MEMORY;
/* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
- if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
- || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
- return X86_64_INTEGERSI_CLASS;
- if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
- || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
- return X86_64_INTEGER_CLASS;
-
- /* Rule (e): If one of the classes is X87 or X87UP class, MEMORY is
- used as class. */
- if (class1 == X86_64_X87_CLASS || class1 == X86_64_X87UP_CLASS
- || class2 == X86_64_X87_CLASS || class2 == X86_64_X87UP_CLASS)
- return X86_64_MEMORY_CLASS;
+ if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
+ return AMD64_INTEGER;
+
+ /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
+ MEMORY is used as class. */
+ if (class1 == AMD64_X87 || class1 == AMD64_X87UP
+ || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
+ || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
+ return AMD64_MEMORY;
/* Rule (f): Otherwise class SSE is used. */
- return X86_64_SSE_CLASS;
+ return AMD64_SSE;
}
-/* Classify the argument type. CLASSES will be filled by the register
- class used to pass each word of the operand. The number of words
- is returned. In case the parameter should be passed in memory, 0
- is returned. As a special case for zero sized containers,
- classes[0] will be NO_CLASS and 1 is returned.
+static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
- See the System V psABI for details. */
+/* Return non-zero if TYPE is a non-POD structure or union type. */
static int
-classify_argument (struct type *type,
- enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
+amd64_non_pod_p (struct type *type)
+{
+ /* ??? A class with a base class certainly isn't POD, but does this
+ catch all non-POD structure types? */
+ if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
+ return 1;
+
+ return 0;
+}
+
+/* Classify TYPE according to the rules for aggregate (structures and
+ arrays) and union types, and store the result in CLASS. */
+
+static void
+amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
{
- int bytes = TYPE_LENGTH (type);
- int words = (bytes + 8 - 1) / 8;
+ int len = TYPE_LENGTH (type);
- switch (TYPE_CODE (type))
+ /* 1. If the size of an object is larger than two eightbytes, or in
+ C++, is a non-POD structure or union type, or contains
+ unaligned fields, it has class memory. */
+ if (len > 16 || amd64_non_pod_p (type))
{
- case TYPE_CODE_ARRAY:
- case TYPE_CODE_STRUCT:
- case TYPE_CODE_UNION:
- {
- int i;
- enum x86_64_reg_class subclasses[MAX_CLASSES];
-
- /* On x86-64 we pass structures larger than 16 bytes on the stack. */
- if (bytes > 16)
- return 0;
-
- for (i = 0; i < words; i++)
- classes[i] = X86_64_NO_CLASS;
-
- /* Zero sized arrays or structures are NO_CLASS. We return 0
- to signalize memory class, so handle it as special case. */
- if (!words)
- {
- classes[0] = X86_64_NO_CLASS;
- return 1;
- }
- switch (TYPE_CODE (type))
- {
- case TYPE_CODE_STRUCT:
- {
- int j;
- for (j = 0; j < TYPE_NFIELDS (type); ++j)
- {
- int num = classify_argument (TYPE_FIELDS (type)[j].type,
- subclasses,
- (TYPE_FIELDS (type)[j].loc.
- bitpos + bit_offset) % 256);
- if (!num)
- return 0;
- for (i = 0; i < num; i++)
- {
- int pos =
- (TYPE_FIELDS (type)[j].loc.bitpos +
- bit_offset) / 8 / 8;
- classes[i + pos] =
- merge_classes (subclasses[i], classes[i + pos]);
- }
- }
- }
- break;
- case TYPE_CODE_ARRAY:
- {
- int num;
+ class[0] = class[1] = AMD64_MEMORY;
+ return;
+ }
- num = classify_argument (TYPE_TARGET_TYPE (type),
- subclasses, bit_offset);
- if (!num)
- return 0;
+ /* 2. Both eightbytes get initialized to class NO_CLASS. */
+ class[0] = class[1] = AMD64_NO_CLASS;
- /* The partial classes are now full classes. */
- if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
- subclasses[0] = X86_64_SSE_CLASS;
- if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
- subclasses[0] = X86_64_INTEGER_CLASS;
+ /* 3. Each field of an object is classified recursively so that
+ always two fields are considered. The resulting class is
+ calculated according to the classes of the fields in the
+ eightbyte: */
- for (i = 0; i < words; i++)
- classes[i] = subclasses[i % num];
- }
- break;
- case TYPE_CODE_UNION:
- {
- int j;
- {
- for (j = 0; j < TYPE_NFIELDS (type); ++j)
- {
- int num;
- num = classify_argument (TYPE_FIELDS (type)[j].type,
- subclasses, bit_offset);
- if (!num)
- return 0;
- for (i = 0; i < num; i++)
- classes[i] = merge_classes (subclasses[i], classes[i]);
- }
- }
- }
- break;
- default:
- break;
- }
- /* Final merger cleanup. */
- for (i = 0; i < words; i++)
- {
- /* If one class is MEMORY, everything should be passed in
- memory. */
- if (classes[i] == X86_64_MEMORY_CLASS)
- return 0;
-
- /* The X86_64_SSEUP_CLASS should be always preceeded by
- X86_64_SSE_CLASS. */
- if (classes[i] == X86_64_SSEUP_CLASS
- && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
- classes[i] = X86_64_SSE_CLASS;
-
- /* X86_64_X87UP_CLASS should be preceeded by X86_64_X87_CLASS. */
- if (classes[i] == X86_64_X87UP_CLASS
- && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
- classes[i] = X86_64_SSE_CLASS;
- }
- return words;
- }
- break;
- case TYPE_CODE_FLT:
- switch (bytes)
- {
- case 4:
- if (!(bit_offset % 64))
- classes[0] = X86_64_SSESF_CLASS;
- else
- classes[0] = X86_64_SSE_CLASS;
- return 1;
- case 8:
- classes[0] = X86_64_SSEDF_CLASS;
- return 1;
- case 16:
- classes[0] = X86_64_X87_CLASS;
- classes[1] = X86_64_X87UP_CLASS;
- return 2;
- }
- break;
- case TYPE_CODE_ENUM:
- case TYPE_CODE_REF:
- case TYPE_CODE_INT:
- case TYPE_CODE_PTR:
- switch (bytes)
+ if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
+ {
+ struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
+
+ /* All fields in an array have the same type. */
+ amd64_classify (subtype, class);
+ if (len > 8 && class[1] == AMD64_NO_CLASS)
+ class[1] = class[0];
+ }
+ else
+ {
+ int i;
+
+ /* Structure or union. */
+ gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
+ || TYPE_CODE (type) == TYPE_CODE_UNION);
+
+ for (i = 0; i < TYPE_NFIELDS (type); i++)
{
- case 1:
- case 2:
- case 4:
- case 8:
- if (bytes * 8 + bit_offset <= 32)
- classes[0] = X86_64_INTEGERSI_CLASS;
- else
- classes[0] = X86_64_INTEGER_CLASS;
- return 1;
- case 16:
- classes[0] = classes[1] = X86_64_INTEGER_CLASS;
- return 2;
- default:
- break;
+ struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
+ int pos = TYPE_FIELD_BITPOS (type, i) / 64;
+ enum amd64_reg_class subclass[2];
+
+ /* Ignore static fields. */
+ if (TYPE_FIELD_STATIC (type, i))
+ continue;
+
+ gdb_assert (pos == 0 || pos == 1);
+
+ amd64_classify (subtype, subclass);
+ class[pos] = amd64_merge_classes (class[pos], subclass[0]);
+ if (pos == 0)
+ class[1] = amd64_merge_classes (class[1], subclass[1]);
}
- case TYPE_CODE_VOID:
- return 0;
- default: /* Avoid warning. */
- break;
}
- internal_error (__FILE__, __LINE__,
- "classify_argument: unknown argument type");
+
+ /* 4. Then a post merger cleanup is done: */
+
+ /* Rule (a): If one of the classes is MEMORY, the whole argument is
+ passed in memory. */
+ if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
+ class[0] = class[1] = AMD64_MEMORY;
+
+ /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
+ SSE. */
+ if (class[0] == AMD64_SSEUP)
+ class[0] = AMD64_SSE;
+ if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
+ class[1] = AMD64_SSE;
}
-/* Examine the argument and set *INT_NREGS and *SSE_NREGS to the
- number of registers required based on the information passed in
- CLASSES. Return 0 if parameter should be passed in memory. */
+/* Classify TYPE, and store the result in CLASS. */
-static int
-examine_argument (enum x86_64_reg_class classes[MAX_CLASSES],
- int n, int *int_nregs, int *sse_nregs)
+static void
+amd64_classify (struct type *type, enum amd64_reg_class class[2])
{
- *int_nregs = 0;
- *sse_nregs = 0;
- if (!n)
- return 0;
- for (n--; n >= 0; n--)
- switch (classes[n])
- {
- case X86_64_INTEGER_CLASS:
- case X86_64_INTEGERSI_CLASS:
- (*int_nregs)++;
- break;
- case X86_64_SSE_CLASS:
- case X86_64_SSESF_CLASS:
- case X86_64_SSEDF_CLASS:
- (*sse_nregs)++;
- break;
- case X86_64_NO_CLASS:
- case X86_64_SSEUP_CLASS:
- case X86_64_X87_CLASS:
- case X86_64_X87UP_CLASS:
- break;
- case X86_64_MEMORY_CLASS:
- internal_error (__FILE__, __LINE__,
- "examine_argument: unexpected memory class");
- }
- return 1;
+ enum type_code code = TYPE_CODE (type);
+ int len = TYPE_LENGTH (type);
+
+ class[0] = class[1] = AMD64_NO_CLASS;
+
+ /* Arguments of types (signed and unsigned) _Bool, char, short, int,
+ long, long long, and pointers are in the INTEGER class. */
+ if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
+ || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
+ && (len == 1 || len == 2 || len == 4 || len == 8))
+ class[0] = AMD64_INTEGER;
+
+ /* Arguments of types float, double and __m64 are in class SSE. */
+ else if (code == TYPE_CODE_FLT && (len == 4 || len == 8))
+ /* FIXME: __m64 . */
+ class[0] = AMD64_SSE;
+
+ /* Arguments of types __float128 and __m128 are split into two
+ halves. The least significant ones belong to class SSE, the most
+ significant one to class SSEUP. */
+ /* FIXME: __float128, __m128. */
+
+ /* The 64-bit mantissa of arguments of type long double belongs to
+ class X87, the 16-bit exponent plus 6 bytes of padding belongs to
+ class X87UP. */
+ else if (code == TYPE_CODE_FLT && len == 16)
+ /* Class X87 and X87UP. */
+ class[0] = AMD64_X87, class[1] = AMD64_X87UP;
+
+ /* Aggregates. */
+ else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
+ || code == TYPE_CODE_UNION)
+ amd64_classify_aggregate (type, class);
}
-#define RET_INT_REGS 2
-#define RET_SSE_REGS 2
+static enum return_value_convention
+amd64_return_value (struct gdbarch *gdbarch, struct type *type,
+ struct regcache *regcache,
+ void *readbuf, const void *writebuf)
+{
+ enum amd64_reg_class class[2];
+ int len = TYPE_LENGTH (type);
+ static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
+ static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
+ int integer_reg = 0;
+ int sse_reg = 0;
+ int i;
-/* Check if the structure in value_type is returned in registers or in
- memory. If this function returns 1, GDB will call
- STORE_STRUCT_RETURN and EXTRACT_STRUCT_VALUE_ADDRESS else
- STORE_RETURN_VALUE and EXTRACT_RETURN_VALUE will be used. */
+ gdb_assert (!(readbuf && writebuf));
-static int
-x86_64_use_struct_convention (int gcc_p, struct type *value_type)
-{
- enum x86_64_reg_class class[MAX_CLASSES];
- int n = classify_argument (value_type, class, 0);
- int needed_intregs;
- int needed_sseregs;
-
- return (!n ||
- !examine_argument (class, n, &needed_intregs, &needed_sseregs) ||
- needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS);
-}
+ /* 1. Classify the return type with the classification algorithm. */
+ amd64_classify (type, class);
-/* Extract from an array REGBUF containing the (raw) register state, a
- function return value of TYPE, and copy that, in virtual format,
- into VALBUF. */
+ /* 2. If the type has class MEMORY, then the caller provides space
+ for the return value and passes the address of this storage in
+ %rdi as if it were the first argument to the function. In
+ effect, this address becomes a hidden first argument. */
+ if (class[0] == AMD64_MEMORY)
+ return RETURN_VALUE_STRUCT_CONVENTION;
-static void
-x86_64_extract_return_value (struct type *type, struct regcache *regcache,
- void *valbuf)
-{
- enum x86_64_reg_class class[MAX_CLASSES];
- int n = classify_argument (type, class, 0);
- int needed_intregs;
- int needed_sseregs;
- int intreg = 0;
- int ssereg = 0;
- int offset = 0;
- int ret_int_r[RET_INT_REGS] = { X86_64_RAX_REGNUM, X86_64_RDX_REGNUM };
- int ret_sse_r[RET_SSE_REGS] = { X86_64_XMM0_REGNUM, X86_64_XMM1_REGNUM };
-
- if (!n ||
- !examine_argument (class, n, &needed_intregs, &needed_sseregs) ||
- needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS)
- { /* memory class */
- CORE_ADDR addr;
- regcache_cooked_read (regcache, X86_64_RAX_REGNUM, &addr);
- read_memory (addr, valbuf, TYPE_LENGTH (type));
- return;
- }
- else
+ gdb_assert (class[1] != AMD64_MEMORY);
+ gdb_assert (len <= 16);
+
+ for (i = 0; len > 0; i++, len -= 8)
{
- int i;
- for (i = 0; i < n; i++)
+ int regnum = -1;
+ int offset = 0;
+
+ switch (class[i])
{
- switch (class[i])
- {
- case X86_64_NO_CLASS:
- break;
- case X86_64_INTEGER_CLASS:
- regcache_cooked_read (regcache, ret_int_r[(intreg + 1) / 2],
- (char *) valbuf + offset);
- offset += 8;
- intreg += 2;
- break;
- case X86_64_INTEGERSI_CLASS:
- regcache_cooked_read_part (regcache, ret_int_r[intreg / 2],
- 0, 4, (char *) valbuf + offset);
- offset += 8;
- intreg++;
- break;
- case X86_64_SSEDF_CLASS:
- case X86_64_SSESF_CLASS:
- case X86_64_SSE_CLASS:
- regcache_cooked_read_part (regcache,
- ret_sse_r[(ssereg + 1) / 2], 0, 8,
- (char *) valbuf + offset);
- offset += 8;
- ssereg += 2;
- break;
- case X86_64_SSEUP_CLASS:
- regcache_cooked_read_part (regcache, ret_sse_r[ssereg / 2],
- 0, 8, (char *) valbuf + offset);
- offset += 8;
- ssereg++;
- break;
- case X86_64_X87_CLASS:
- regcache_cooked_read_part (regcache, X86_64_ST0_REGNUM,
- 0, 8, (char *) valbuf + offset);
- offset += 8;
- break;
- case X86_64_X87UP_CLASS:
- regcache_cooked_read_part (regcache, X86_64_ST0_REGNUM,
- 8, 2, (char *) valbuf + offset);
- offset += 8;
- break;
- case X86_64_MEMORY_CLASS:
- default:
- internal_error (__FILE__, __LINE__,
- "Unexpected argument class");
- }
+ case AMD64_INTEGER:
+ /* 3. If the class is INTEGER, the next available register
+ of the sequence %rax, %rdx is used. */
+ regnum = integer_regnum[integer_reg++];
+ break;
+
+ case AMD64_SSE:
+ /* 4. If the class is SSE, the next available SSE register
+ of the sequence %xmm0, %xmm1 is used. */
+ regnum = sse_regnum[sse_reg++];
+ break;
+
+ case AMD64_SSEUP:
+ /* 5. If the class is SSEUP, the eightbyte is passed in the
+ upper half of the last used SSE register. */
+ gdb_assert (sse_reg > 0);
+ regnum = sse_regnum[sse_reg - 1];
+ offset = 8;
+ break;
+
+ case AMD64_X87:
+ /* 6. If the class is X87, the value is returned on the X87
+ stack in %st0 as 80-bit x87 number. */
+ regnum = AMD64_ST0_REGNUM;
+ if (writebuf)
+ i387_return_value (gdbarch, regcache);
+ break;
+
+ case AMD64_X87UP:
+ /* 7. If the class is X87UP, the value is returned together
+ with the previous X87 value in %st0. */
+ gdb_assert (i > 0 && class[0] == AMD64_X87);
+ regnum = AMD64_ST0_REGNUM;
+ offset = 8;
+ len = 2;
+ break;
+
+ case AMD64_NO_CLASS:
+ continue;
+
+ default:
+ gdb_assert (!"Unexpected register class.");
}
+
+ gdb_assert (regnum != -1);
+
+ if (readbuf)
+ regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
+ (char *) readbuf + i * 8);
+ if (writebuf)
+ regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
+ (const char *) writebuf + i * 8);
}
-}
-#define INT_REGS 6
-#define SSE_REGS 8
+ return RETURN_VALUE_REGISTER_CONVENTION;
+}
+\f
static CORE_ADDR
-x86_64_push_arguments (struct regcache *regcache, int nargs,
- struct value **args, CORE_ADDR sp)
+amd64_push_arguments (struct regcache *regcache, int nargs,
+ struct value **args, CORE_ADDR sp, int struct_return)
{
- int intreg = 0;
- int ssereg = 0;
- int i;
- static int int_parameter_registers[INT_REGS] =
+ static int integer_regnum[] =
{
- X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */
- X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */
- 8, 9 /* %r8, %r9 */
+ AMD64_RDI_REGNUM, /* %rdi */
+ AMD64_RSI_REGNUM, /* %rsi */
+ AMD64_RDX_REGNUM, /* %rdx */
+ AMD64_RCX_REGNUM, /* %rcx */
+ 8, /* %r8 */
+ 9 /* %r9 */
};
- /* %xmm0 - %xmm7 */
- static int sse_parameter_registers[SSE_REGS] =
+ static int sse_regnum[] =
{
- X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
- X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
- X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
- X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
+ /* %xmm0 ... %xmm7 */
+ AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
+ AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
+ AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
+ AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
};
- int stack_values_count = 0;
- int *stack_values;
- stack_values = alloca (nargs * sizeof (int));
+ struct value **stack_args = alloca (nargs * sizeof (struct value *));
+ int num_stack_args = 0;
+ int num_elements = 0;
+ int element = 0;
+ int integer_reg = 0;
+ int sse_reg = 0;
+ int i;
+
+ /* Reserve a register for the "hidden" argument. */
+ if (struct_return)
+ integer_reg++;
+
for (i = 0; i < nargs; i++)
{
- enum x86_64_reg_class class[MAX_CLASSES];
- int n = classify_argument (args[i]->type, class, 0);
- int needed_intregs;
- int needed_sseregs;
-
- if (!n ||
- !examine_argument (class, n, &needed_intregs, &needed_sseregs)
- || intreg / 2 + needed_intregs > INT_REGS
- || ssereg / 2 + needed_sseregs > SSE_REGS)
- { /* memory class */
- stack_values[stack_values_count++] = i;
+ struct type *type = VALUE_TYPE (args[i]);
+ int len = TYPE_LENGTH (type);
+ enum amd64_reg_class class[2];
+ int needed_integer_regs = 0;
+ int needed_sse_regs = 0;
+ int j;
+
+ /* Classify argument. */
+ amd64_classify (type, class);
+
+ /* Calculate the number of integer and SSE registers needed for
+ this argument. */
+ for (j = 0; j < 2; j++)
+ {
+ if (class[j] == AMD64_INTEGER)
+ needed_integer_regs++;
+ else if (class[j] == AMD64_SSE)
+ needed_sse_regs++;
+ }
+
+ /* Check whether enough registers are available, and if the
+ argument should be passed in registers at all. */
+ if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
+ || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
+ || (needed_integer_regs == 0 && needed_sse_regs == 0))
+ {
+ /* The argument will be passed on the stack. */
+ num_elements += ((len + 7) / 8);
+ stack_args[num_stack_args++] = args[i];
}
else
{
- int j;
- for (j = 0; j < n; j++)
+ /* The argument will be passed in registers. */
+ char *valbuf = VALUE_CONTENTS (args[i]);
+ char buf[8];
+
+ gdb_assert (len <= 16);
+
+ for (j = 0; len > 0; j++, len -= 8)
{
+ int regnum = -1;
int offset = 0;
+
switch (class[j])
{
- case X86_64_NO_CLASS:
- break;
- case X86_64_INTEGER_CLASS:
- regcache_cooked_write
- (regcache, int_parameter_registers[(intreg + 1) / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- intreg += 2;
- break;
- case X86_64_INTEGERSI_CLASS:
- {
- LONGEST val = extract_signed_integer
- (VALUE_CONTENTS_ALL (args[i]) + offset, 4);
- regcache_cooked_write_signed
- (regcache, int_parameter_registers[intreg / 2], val);
-
- offset += 8;
- intreg++;
- break;
- }
- case X86_64_SSEDF_CLASS:
- case X86_64_SSESF_CLASS:
- case X86_64_SSE_CLASS:
- regcache_cooked_write
- (regcache, sse_parameter_registers[(ssereg + 1) / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- ssereg += 2;
+ case AMD64_INTEGER:
+ regnum = integer_regnum[integer_reg++];
break;
- case X86_64_SSEUP_CLASS:
- regcache_cooked_write
- (regcache, sse_parameter_registers[ssereg / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- ssereg++;
- break;
- case X86_64_X87_CLASS:
- case X86_64_MEMORY_CLASS:
- stack_values[stack_values_count++] = i;
+
+ case AMD64_SSE:
+ regnum = sse_regnum[sse_reg++];
break;
- case X86_64_X87UP_CLASS:
+
+ case AMD64_SSEUP:
+ gdb_assert (sse_reg > 0);
+ regnum = sse_regnum[sse_reg - 1];
+ offset = 8;
break;
+
default:
- internal_error (__FILE__, __LINE__,
- "Unexpected argument class");
+ gdb_assert (!"Unexpected register class.");
}
- intreg += intreg % 2;
- ssereg += ssereg % 2;
+
+ gdb_assert (regnum != -1);
+ memset (buf, 0, sizeof buf);
+ memcpy (buf, valbuf + j * 8, min (len, 8));
+ regcache_raw_write_part (regcache, regnum, offset, 8, buf);
}
}
}
- /* Push any remaining arguments onto the stack. */
- while (--stack_values_count >= 0)
- {
- struct value *arg = args[stack_values[stack_values_count]];
- int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
-
- /* Make sure the stack stays eightbyte-aligned. */
- sp -= (len + 7) & ~7;
- write_memory (sp, VALUE_CONTENTS_ALL (arg), len);
- }
-
- return sp;
-}
+ /* Allocate space for the arguments on the stack. */
+ sp -= num_elements * 8;
-/* Write into the appropriate registers a function return value stored
- in VALBUF of type TYPE, given in virtual format. */
-
-static void
-x86_64_store_return_value (struct type *type, struct regcache *regcache,
- const void *valbuf)
-{
- int len = TYPE_LENGTH (type);
+ /* The psABI says that "The end of the input argument area shall be
+ aligned on a 16 byte boundary." */
+ sp &= ~0xf;
- if (TYPE_CODE_FLT == TYPE_CODE (type))
- {
- ULONGEST fstat;
- char buf[FPU_REG_RAW_SIZE];
-
- /* Returning floating-point values is a bit tricky. Apart from
- storing the return value in %st(0), we have to simulate the
- state of the FPU at function return point. */
-
- /* Convert the value found in VALBUF to the extended
- floating-point format used by the FPU. This is probably
- not exactly how it would happen on the target itself, but
- it is the best we can do. */
- convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext);
- regcache_raw_write (regcache, X86_64_ST0_REGNUM, buf);
-
- /* Set the top of the floating-point register stack to 7. The
- actual value doesn't really matter, but 7 is what a normal
- function return would end up with if the program started out
- with a freshly initialized FPU. */
- regcache_raw_read_unsigned (regcache, FSTAT_REGNUM, &fstat);
- fstat |= (7 << 11);
- regcache_raw_write_unsigned (regcache, FSTAT_REGNUM, fstat);
-
- /* Mark %st(1) through %st(7) as empty. Since we set the top of
- the floating-point register stack to 7, the appropriate value
- for the tag word is 0x3fff. */
- regcache_raw_write_unsigned (regcache, FTAG_REGNUM, 0x3fff);
- }
- else
+ /* Write out the arguments to the stack. */
+ for (i = 0; i < num_stack_args; i++)
{
- int low_size = REGISTER_RAW_SIZE (0);
- int high_size = REGISTER_RAW_SIZE (1);
+ struct type *type = VALUE_TYPE (stack_args[i]);
+ char *valbuf = VALUE_CONTENTS (stack_args[i]);
+ int len = TYPE_LENGTH (type);
- if (len <= low_size)
- regcache_cooked_write_part (regcache, 0, 0, len, valbuf);
- else if (len <= (low_size + high_size))
- {
- regcache_cooked_write_part (regcache, 0, 0, low_size, valbuf);
- regcache_cooked_write_part (regcache, 1, 0,
- len - low_size,
- (const char *) valbuf + low_size);
- }
- else
- internal_error (__FILE__, __LINE__,
- "Cannot store return value of %d bytes long.", len);
+ write_memory (sp + element * 8, valbuf, len);
+ element += ((len + 7) / 8);
}
+
+ /* The psABI says that "For calls that may call functions that use
+ varargs or stdargs (prototype-less calls or calls to functions
+ containing ellipsis (...) in the declaration) %al is used as
+ hidden argument to specify the number of SSE registers used. */
+ regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
+ return sp;
}
-\f
static CORE_ADDR
-x86_64_push_dummy_call (struct gdbarch *gdbarch, struct regcache *regcache,
- CORE_ADDR dummy_addr, int nargs, struct value **args,
- CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
+amd64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
{
char buf[8];
/* Pass arguments. */
- sp = x86_64_push_arguments (regcache, nargs, args, sp);
+ sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
/* Pass "hidden" argument". */
if (struct_return)
{
store_unsigned_integer (buf, 8, struct_addr);
- regcache_cooked_write (regcache, X86_64_RDI_REGNUM, buf);
+ regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
}
/* Store return address. */
sp -= 8;
- store_unsigned_integer (buf, 8, dummy_addr);
+ store_unsigned_integer (buf, 8, bp_addr);
write_memory (sp, buf, 8);
/* Finally, update the stack pointer... */
store_unsigned_integer (buf, 8, sp);
- regcache_cooked_write (regcache, X86_64_RSP_REGNUM, buf);
+ regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
/* ...and fake a frame pointer. */
- regcache_cooked_write (regcache, X86_64_RBP_REGNUM, buf);
+ regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
- return sp;
+ return sp + 16;
}
\f
/* The maximum number of saved registers. This should include %rip. */
-#define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS
+#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
-struct x86_64_frame_cache
+struct amd64_frame_cache
{
/* Base address. */
CORE_ADDR base;
CORE_ADDR pc;
/* Saved registers. */
- CORE_ADDR saved_regs[X86_64_NUM_SAVED_REGS];
+ CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
CORE_ADDR saved_sp;
/* Do we have a frame? */
/* Allocate and initialize a frame cache. */
-static struct x86_64_frame_cache *
-x86_64_alloc_frame_cache (void)
+static struct amd64_frame_cache *
+amd64_alloc_frame_cache (void)
{
- struct x86_64_frame_cache *cache;
+ struct amd64_frame_cache *cache;
int i;
- cache = FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache);
+ cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
/* Base address. */
cache->base = 0;
/* Saved registers. We initialize these to -1 since zero is a valid
offset (that's where %rbp is supposed to be stored). */
- for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
+ for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
cache->saved_regs[i] = -1;
cache->saved_sp = 0;
to have no prologue and thus no valid frame pointer in %rbp. */
static CORE_ADDR
-x86_64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
- struct x86_64_frame_cache *cache)
+amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
+ struct amd64_frame_cache *cache)
{
static unsigned char proto[3] = { 0x48, 0x89, 0xe5 };
unsigned char buf[3];
{
/* Take into account that we've executed the `pushq %rbp' that
starts this instruction sequence. */
- cache->saved_regs[X86_64_RBP_REGNUM] = 0;
+ cache->saved_regs[AMD64_RBP_REGNUM] = 0;
cache->sp_offset += 8;
/* If that's all, return now. */
/* Return PC of first real instruction. */
static CORE_ADDR
-x86_64_skip_prologue (CORE_ADDR start_pc)
+amd64_skip_prologue (CORE_ADDR start_pc)
{
- struct x86_64_frame_cache cache;
+ struct amd64_frame_cache cache;
CORE_ADDR pc;
- pc = x86_64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache);
+ pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache);
if (cache.frameless_p)
return start_pc;
/* Normal frames. */
-static struct x86_64_frame_cache *
-x86_64_frame_cache (struct frame_info *next_frame, void **this_cache)
+static struct amd64_frame_cache *
+amd64_frame_cache (struct frame_info *next_frame, void **this_cache)
{
- struct x86_64_frame_cache *cache;
+ struct amd64_frame_cache *cache;
char buf[8];
int i;
if (*this_cache)
return *this_cache;
- cache = x86_64_alloc_frame_cache ();
+ cache = amd64_alloc_frame_cache ();
*this_cache = cache;
- frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
- cache->base = extract_unsigned_integer (buf, 8);
- if (cache->base == 0)
- return cache;
-
- /* For normal frames, %rip is stored at 8(%rbp). */
- cache->saved_regs[X86_64_RIP_REGNUM] = 8;
-
cache->pc = frame_func_unwind (next_frame);
if (cache->pc != 0)
- x86_64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
+ amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
if (cache->frameless_p)
{
frame by looking at the stack pointer. For truly "frameless"
functions this might work too. */
- frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
+ frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
}
+ else
+ {
+ frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
+ cache->base = extract_unsigned_integer (buf, 8);
+ }
/* Now that we have the base address for the stack frame we can
calculate the value of %rsp in the calling frame. */
cache->saved_sp = cache->base + 16;
+ /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
+ frame we find it at the same offset from the reconstructed base
+ address. */
+ cache->saved_regs[AMD64_RIP_REGNUM] = 8;
+
/* Adjust all the saved registers such that they contain addresses
instead of offsets. */
- for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
+ for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
if (cache->saved_regs[i] != -1)
cache->saved_regs[i] += cache->base;
}
static void
-x86_64_frame_this_id (struct frame_info *next_frame, void **this_cache,
- struct frame_id *this_id)
+amd64_frame_this_id (struct frame_info *next_frame, void **this_cache,
+ struct frame_id *this_id)
{
- struct x86_64_frame_cache *cache =
- x86_64_frame_cache (next_frame, this_cache);
+ struct amd64_frame_cache *cache =
+ amd64_frame_cache (next_frame, this_cache);
/* This marks the outermost frame. */
if (cache->base == 0)
}
static void
-x86_64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
- int regnum, int *optimizedp,
- enum lval_type *lvalp, CORE_ADDR *addrp,
- int *realnump, void *valuep)
+amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
+ int regnum, int *optimizedp,
+ enum lval_type *lvalp, CORE_ADDR *addrp,
+ int *realnump, void *valuep)
{
- struct x86_64_frame_cache *cache =
- x86_64_frame_cache (next_frame, this_cache);
+ struct amd64_frame_cache *cache =
+ amd64_frame_cache (next_frame, this_cache);
gdb_assert (regnum >= 0);
return;
}
- if (regnum < X86_64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
+ if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
{
*optimizedp = 0;
*lvalp = lval_memory;
optimizedp, lvalp, addrp, realnump, valuep);
}
-static const struct frame_unwind x86_64_frame_unwind =
+static const struct frame_unwind amd64_frame_unwind =
{
NORMAL_FRAME,
- x86_64_frame_this_id,
- x86_64_frame_prev_register
+ amd64_frame_this_id,
+ amd64_frame_prev_register
};
static const struct frame_unwind *
-x86_64_frame_p (CORE_ADDR pc)
+amd64_frame_sniffer (struct frame_info *next_frame)
{
- return &x86_64_frame_unwind;
+ return &amd64_frame_unwind;
}
\f
64-bit variants. This would require using identical frame caches
on both platforms. */
-static struct x86_64_frame_cache *
-x86_64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
+static struct amd64_frame_cache *
+amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
{
- struct x86_64_frame_cache *cache;
+ struct amd64_frame_cache *cache;
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
CORE_ADDR addr;
char buf[8];
if (*this_cache)
return *this_cache;
- cache = x86_64_alloc_frame_cache ();
+ cache = amd64_alloc_frame_cache ();
- frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
+ frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 8) - 8;
addr = tdep->sigcontext_addr (next_frame);
gdb_assert (tdep->sc_reg_offset);
- gdb_assert (tdep->sc_num_regs <= X86_64_NUM_SAVED_REGS);
+ gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
for (i = 0; i < tdep->sc_num_regs; i++)
if (tdep->sc_reg_offset[i] != -1)
cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
}
static void
-x86_64_sigtramp_frame_this_id (struct frame_info *next_frame,
- void **this_cache, struct frame_id *this_id)
+amd64_sigtramp_frame_this_id (struct frame_info *next_frame,
+ void **this_cache, struct frame_id *this_id)
{
- struct x86_64_frame_cache *cache =
- x86_64_sigtramp_frame_cache (next_frame, this_cache);
+ struct amd64_frame_cache *cache =
+ amd64_sigtramp_frame_cache (next_frame, this_cache);
(*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
}
static void
-x86_64_sigtramp_frame_prev_register (struct frame_info *next_frame,
- void **this_cache,
- int regnum, int *optimizedp,
- enum lval_type *lvalp, CORE_ADDR *addrp,
- int *realnump, void *valuep)
+amd64_sigtramp_frame_prev_register (struct frame_info *next_frame,
+ void **this_cache,
+ int regnum, int *optimizedp,
+ enum lval_type *lvalp, CORE_ADDR *addrp,
+ int *realnump, void *valuep)
{
/* Make sure we've initialized the cache. */
- x86_64_sigtramp_frame_cache (next_frame, this_cache);
+ amd64_sigtramp_frame_cache (next_frame, this_cache);
- x86_64_frame_prev_register (next_frame, this_cache, regnum,
- optimizedp, lvalp, addrp, realnump, valuep);
+ amd64_frame_prev_register (next_frame, this_cache, regnum,
+ optimizedp, lvalp, addrp, realnump, valuep);
}
-static const struct frame_unwind x86_64_sigtramp_frame_unwind =
+static const struct frame_unwind amd64_sigtramp_frame_unwind =
{
SIGTRAMP_FRAME,
- x86_64_sigtramp_frame_this_id,
- x86_64_sigtramp_frame_prev_register
+ amd64_sigtramp_frame_this_id,
+ amd64_sigtramp_frame_prev_register
};
static const struct frame_unwind *
-x86_64_sigtramp_frame_p (CORE_ADDR pc)
+amd64_sigtramp_frame_sniffer (struct frame_info *next_frame)
{
+ CORE_ADDR pc = frame_pc_unwind (next_frame);
char *name;
find_pc_partial_function (pc, &name, NULL, NULL);
if (PC_IN_SIGTRAMP (pc, name))
- return &x86_64_sigtramp_frame_unwind;
+ {
+ gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr);
+
+ return &amd64_sigtramp_frame_unwind;
+ }
return NULL;
}
\f
static CORE_ADDR
-x86_64_frame_base_address (struct frame_info *next_frame, void **this_cache)
+amd64_frame_base_address (struct frame_info *next_frame, void **this_cache)
{
- struct x86_64_frame_cache *cache =
- x86_64_frame_cache (next_frame, this_cache);
+ struct amd64_frame_cache *cache =
+ amd64_frame_cache (next_frame, this_cache);
return cache->base;
}
-static const struct frame_base x86_64_frame_base =
+static const struct frame_base amd64_frame_base =
{
- &x86_64_frame_unwind,
- x86_64_frame_base_address,
- x86_64_frame_base_address,
- x86_64_frame_base_address
+ &amd64_frame_unwind,
+ amd64_frame_base_address,
+ amd64_frame_base_address,
+ amd64_frame_base_address
};
-static void
-x86_64_save_dummy_frame_tos (CORE_ADDR sp)
-{
- generic_save_dummy_frame_tos (sp + 16);
-}
-
static struct frame_id
-x86_64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
+amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
char buf[8];
CORE_ADDR fp;
- frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
+ frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
fp = extract_unsigned_integer (buf, 8);
return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
}
+/* 16 byte align the SP per frame requirements. */
+
+static CORE_ADDR
+amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
+{
+ return sp & -(CORE_ADDR)16;
+}
+\f
+
+/* Supply register REGNUM from the floating-point register set REGSET
+ to register cache REGCACHE. If REGNUM is -1, do this for all
+ registers in REGSET. */
+
+static void
+amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *fpregs, size_t len)
+{
+ const struct gdbarch_tdep *tdep = regset->descr;
+
+ gdb_assert (len == tdep->sizeof_fpregset);
+ amd64_supply_fxsave (regcache, regnum, fpregs);
+}
+
+/* Return the appropriate register set for the core section identified
+ by SECT_NAME and SECT_SIZE. */
+
+static const struct regset *
+amd64_regset_from_core_section (struct gdbarch *gdbarch,
+ const char *sect_name, size_t sect_size)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
+ {
+ if (tdep->fpregset == NULL)
+ {
+ tdep->fpregset = XMALLOC (struct regset);
+ tdep->fpregset->descr = tdep;
+ tdep->fpregset->supply_regset = amd64_supply_fpregset;
+ }
+
+ return tdep->fpregset;
+ }
+
+ return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
+}
+\f
+
void
-x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
+amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- /* The x86-64 has 16 SSE registers. */
+ /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
+ floating-point registers. */
+ tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
+
+ /* AMD64 has an FPU and 16 SSE registers. */
+ tdep->st0_regnum = AMD64_ST0_REGNUM;
tdep->num_xmm_regs = 16;
/* This is what all the fuss is about. */
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
- /* In contrast to the i386, on the x86-64 a `long double' actually
- takes up 128 bits, even though it's still based on the i387
- extended floating-point format which has only 80 significant bits. */
+ /* In contrast to the i386, on AMD64 a `long double' actually takes
+ up 128 bits, even though it's still based on the i387 extended
+ floating-point format which has only 80 significant bits. */
set_gdbarch_long_double_bit (gdbarch, 128);
- set_gdbarch_num_regs (gdbarch, X86_64_NUM_REGS);
- set_gdbarch_register_name (gdbarch, x86_64_register_name);
- set_gdbarch_register_type (gdbarch, x86_64_register_type);
+ set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
+ set_gdbarch_register_name (gdbarch, amd64_register_name);
+ set_gdbarch_register_type (gdbarch, amd64_register_type);
/* Register numbers of various important registers. */
- set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */
- set_gdbarch_pc_regnum (gdbarch, X86_64_RIP_REGNUM); /* %rip */
- set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */
- set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */
-
- /* The "default" register numbering scheme for the x86-64 is
- referred to as the "DWARF Register Number Mapping" in the System
- V psABI. The preferred debugging format for all known x86-64
- targets is actually DWARF2, and GCC doesn't seem to support DWARF
- (that is DWARF-1), but we provide the same mapping just in case.
- This mapping is also used for stabs, which GCC does support. */
- set_gdbarch_stab_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
- set_gdbarch_dwarf_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
- set_gdbarch_dwarf2_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
+ set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
+ set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
+ set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
+ set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
+
+ /* The "default" register numbering scheme for AMD64 is referred to
+ as the "DWARF Register Number Mapping" in the System V psABI.
+ The preferred debugging format for all known AMD64 targets is
+ actually DWARF2, and GCC doesn't seem to support DWARF (that is
+ DWARF-1), but we provide the same mapping just in case. This
+ mapping is also used for stabs, which GCC does support. */
+ set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
+ set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
/* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
- be in use on any of the supported x86-64 targets. */
+ be in use on any of the supported AMD64 targets. */
/* Call dummy code. */
- set_gdbarch_push_dummy_call (gdbarch, x86_64_push_dummy_call);
+ set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
+ set_gdbarch_frame_align (gdbarch, amd64_frame_align);
+ set_gdbarch_frame_red_zone_size (gdbarch, 128);
- set_gdbarch_extract_return_value (gdbarch, x86_64_extract_return_value);
- set_gdbarch_store_return_value (gdbarch, x86_64_store_return_value);
- /* Override, since this is handled by x86_64_extract_return_value. */
- set_gdbarch_extract_struct_value_address (gdbarch, NULL);
- set_gdbarch_use_struct_convention (gdbarch, x86_64_use_struct_convention);
+ set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p);
+ set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
+ set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
- set_gdbarch_skip_prologue (gdbarch, x86_64_skip_prologue);
+ set_gdbarch_return_value (gdbarch, amd64_return_value);
+
+ set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
/* Avoid wiring in the MMX registers for now. */
set_gdbarch_num_pseudo_regs (gdbarch, 0);
+ tdep->mm0_regnum = -1;
- set_gdbarch_unwind_dummy_id (gdbarch, x86_64_unwind_dummy_id);
- set_gdbarch_save_dummy_frame_tos (gdbarch, x86_64_save_dummy_frame_tos);
+ set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
/* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
- since all supported x86-64 targets are ELF, but that might change
+ since all supported AMD64 targets are ELF, but that might change
in the future. */
set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section);
- frame_unwind_append_predicate (gdbarch, x86_64_sigtramp_frame_p);
- frame_unwind_append_predicate (gdbarch, x86_64_frame_p);
- frame_base_set_default (gdbarch, &x86_64_frame_base);
+ frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
+ frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
+ frame_base_set_default (gdbarch, &amd64_frame_base);
+
+ /* If we have a register mapping, enable the generic core file support. */
+ if (tdep->gregset_reg_offset)
+ set_gdbarch_regset_from_core_section (gdbarch,
+ amd64_regset_from_core_section);
}
\f
-#define I387_FISEG_REGNUM FISEG_REGNUM
-#define I387_FOSEG_REGNUM FOSEG_REGNUM
+#define I387_ST0_REGNUM AMD64_ST0_REGNUM
/* The 64-bit FXSAVE format differs from the 32-bit format in the
sense that the instruction pointer and data pointer are simply
bits of these pointers (instead of just the 16-bits of the segment
selector). */
-/* Fill GDB's register array with the floating-point and SSE register
- values in *FXSAVE. This function masks off any of the reserved
- bits in *FXSAVE. */
+/* Fill register REGNUM in REGCACHE with the appropriate
+ floating-point or SSE register value from *FXSAVE. If REGNUM is
+ -1, do this for all registers. This function masks off any of the
+ reserved bits in *FXSAVE. */
void
-x86_64_supply_fxsave (char *fxsave)
+amd64_supply_fxsave (struct regcache *regcache, int regnum,
+ const void *fxsave)
{
- i387_supply_fxsave (fxsave);
+ i387_supply_fxsave (regcache, regnum, fxsave);
if (fxsave)
{
- supply_register (I387_FISEG_REGNUM, fxsave + 12);
- supply_register (I387_FOSEG_REGNUM, fxsave + 20);
+ const char *regs = fxsave;
+
+ if (regnum == -1 || regnum == I387_FISEG_REGNUM)
+ regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12);
+ if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
+ regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20);
}
}
/* Fill register REGNUM (if it is a floating-point or SSE register) in
- *FXSAVE with the value in GDB's register array. If REGNUM is -1, do
+ *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
this for all registers. This function doesn't touch any of the
reserved bits in *FXSAVE. */
void
-x86_64_fill_fxsave (char *fxsave, int regnum)
+amd64_fill_fxsave (char *fxsave, int regnum)
{
i387_fill_fxsave (fxsave, regnum);
if (regnum == -1 || regnum == I387_FISEG_REGNUM)
- regcache_collect (regnum, fxsave + 12);
+ regcache_collect (I387_FISEG_REGNUM, fxsave + 12);
if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
- regcache_collect (regnum, fxsave + 20);
+ regcache_collect (I387_FOSEG_REGNUM, fxsave + 20);
}
projects / deliverable / binutils-gdb.git / blobdiff