-/* Target-dependent code for the x86-64 for GDB, the GNU debugger.
+/* Target-dependent code for AMD64.
- Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by Jiri Smid, SuSE Labs.
This file is part of GDB.
#include "x86-64-tdep.h"
#include "i387-tdep.h"
+/* Note that the AMD64 architecture was previously known as x86-64.
+ The latter is (forever) engraved into the canonical system name as
+ returned bu config.guess, and used as the name for the AMD64 port
+ of GNU/Linux. The BSD's have renamed their ports to amd64; they
+ don't like to shout. For GDB we prefer the amd64_-prefix over the
+ x86_64_-prefix since it's so much easier to type. */
+
/* Register information. */
-struct x86_64_register_info
+struct amd64_register_info
{
char *name;
struct type **type;
};
-static struct x86_64_register_info x86_64_register_info[] =
+static struct amd64_register_info amd64_register_info[] =
{
{ "rax", &builtin_type_int64 },
{ "rbx", &builtin_type_int64 },
{ "r15", &builtin_type_int64 },
{ "rip", &builtin_type_void_func_ptr },
{ "eflags", &builtin_type_int32 },
+ { "cs", &builtin_type_int32 },
+ { "ss", &builtin_type_int32 },
{ "ds", &builtin_type_int32 },
{ "es", &builtin_type_int32 },
{ "fs", &builtin_type_int32 },
{ "gs", &builtin_type_int32 },
- /* %st0 is register number 22. */
+ /* %st0 is register number 24. */
{ "st0", &builtin_type_i387_ext },
{ "st1", &builtin_type_i387_ext },
{ "st2", &builtin_type_i387_ext },
{ "fooff", &builtin_type_int32 },
{ "fop", &builtin_type_int32 },
- /* %xmm0 is register number 38. */
+ /* %xmm0 is register number 40. */
{ "xmm0", &builtin_type_v4sf },
{ "xmm1", &builtin_type_v4sf },
{ "xmm2", &builtin_type_v4sf },
};
/* Total number of registers. */
-#define X86_64_NUM_REGS \
- (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0]))
+#define AMD64_NUM_REGS \
+ (sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
/* Return the name of register REGNUM. */
static const char *
-x86_64_register_name (int regnum)
+amd64_register_name (int regnum)
{
- if (regnum >= 0 && regnum < X86_64_NUM_REGS)
- return x86_64_register_info[regnum].name;
+ if (regnum >= 0 && regnum < AMD64_NUM_REGS)
+ return amd64_register_info[regnum].name;
return NULL;
}
register REGNUM. */
static struct type *
-x86_64_register_type (struct gdbarch *gdbarch, int regnum)
+amd64_register_type (struct gdbarch *gdbarch, int regnum)
{
- gdb_assert (regnum >= 0 && regnum < X86_64_NUM_REGS);
+ gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS);
- return *x86_64_register_info[regnum].type;
+ return *amd64_register_info[regnum].type;
}
/* DWARF Register Number Mapping as defined in the System V psABI,
section 3.6. */
-static int x86_64_dwarf_regmap[] =
+static int amd64_dwarf_regmap[] =
{
/* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 2, 1,
/* Extended Integer Registers 8 - 15. */
8, 9, 10, 11, 12, 13, 14, 15,
- /* Return Address RA. Not mapped. */
- -1,
+ /* Return Address RA. Mapped to RIP. */
+ X86_64_RIP_REGNUM,
/* SSE Registers 0 - 7. */
X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7
};
-static const int x86_64_dwarf_regmap_len =
- (sizeof (x86_64_dwarf_regmap) / sizeof (x86_64_dwarf_regmap[0]));
+static const int amd64_dwarf_regmap_len =
+ (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
/* Convert DWARF register number REG to the appropriate register
number used by GDB. */
static int
-x86_64_dwarf_reg_to_regnum (int reg)
+amd64_dwarf_reg_to_regnum (int reg)
{
int regnum = -1;
- if (reg >= 0 || reg < x86_64_dwarf_regmap_len)
- regnum = x86_64_dwarf_regmap[reg];
+ if (reg >= 0 || reg < amd64_dwarf_regmap_len)
+ regnum = amd64_dwarf_regmap[reg];
if (regnum == -1)
warning ("Unmapped DWARF Register #%d encountered\n", reg);
needs any special handling. */
static int
-x86_64_convert_register_p (int regnum, struct type *type)
+amd64_convert_register_p (int regnum, struct type *type)
{
return i386_fp_regnum_p (regnum);
}
\f
-/* The returning of values is done according to the special algorithm.
- Some types are returned in registers an some (big structures) in
- memory. See the System V psABI for details. */
-
-#define MAX_CLASSES 4
-
-enum x86_64_reg_class
-{
- X86_64_NO_CLASS,
- X86_64_INTEGER_CLASS,
- X86_64_INTEGERSI_CLASS,
- X86_64_SSE_CLASS,
- X86_64_SSESF_CLASS,
- X86_64_SSEDF_CLASS,
- X86_64_SSEUP_CLASS,
- X86_64_X87_CLASS,
- X86_64_X87UP_CLASS,
- X86_64_MEMORY_CLASS
-};
-
-/* Return the union class of CLASS1 and CLASS2.
- See the System V psABI for details. */
-
-static enum x86_64_reg_class
-merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
-{
- /* Rule (a): If both classes are equal, this is the resulting class. */
- if (class1 == class2)
- return class1;
-
- /* Rule (b): If one of the classes is NO_CLASS, the resulting class
- is the other class. */
- if (class1 == X86_64_NO_CLASS)
- return class2;
- if (class2 == X86_64_NO_CLASS)
- return class1;
-
- /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
- if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
- return X86_64_MEMORY_CLASS;
-
- /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
- if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
- || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
- return X86_64_INTEGERSI_CLASS;
- if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
- || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
- return X86_64_INTEGER_CLASS;
-
- /* Rule (e): If one of the classes is X87 or X87UP class, MEMORY is
- used as class. */
- if (class1 == X86_64_X87_CLASS || class1 == X86_64_X87UP_CLASS
- || class2 == X86_64_X87_CLASS || class2 == X86_64_X87UP_CLASS)
- return X86_64_MEMORY_CLASS;
-
- /* Rule (f): Otherwise class SSE is used. */
- return X86_64_SSE_CLASS;
-}
-
-/* Classify the argument type. CLASSES will be filled by the register
- class used to pass each word of the operand. The number of words
- is returned. In case the parameter should be passed in memory, 0
- is returned. As a special case for zero sized containers,
- classes[0] will be NO_CLASS and 1 is returned.
-
- See the System V psABI for details. */
-
-static int
-classify_argument (struct type *type,
- enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
-{
- int bytes = TYPE_LENGTH (type);
- int words = (bytes + 8 - 1) / 8;
-
- switch (TYPE_CODE (type))
- {
- case TYPE_CODE_ARRAY:
- case TYPE_CODE_STRUCT:
- case TYPE_CODE_UNION:
- {
- int i;
- enum x86_64_reg_class subclasses[MAX_CLASSES];
-
- /* On x86-64 we pass structures larger than 16 bytes on the stack. */
- if (bytes > 16)
- return 0;
-
- for (i = 0; i < words; i++)
- classes[i] = X86_64_NO_CLASS;
-
- /* Zero sized arrays or structures are NO_CLASS. We return 0
- to signalize memory class, so handle it as special case. */
- if (!words)
- {
- classes[0] = X86_64_NO_CLASS;
- return 1;
- }
- switch (TYPE_CODE (type))
- {
- case TYPE_CODE_STRUCT:
- {
- int j;
- for (j = 0; j < TYPE_NFIELDS (type); ++j)
- {
- int num = classify_argument (TYPE_FIELDS (type)[j].type,
- subclasses,
- (TYPE_FIELDS (type)[j].loc.
- bitpos + bit_offset) % 256);
- if (!num)
- return 0;
- for (i = 0; i < num; i++)
- {
- int pos =
- (TYPE_FIELDS (type)[j].loc.bitpos +
- bit_offset) / 8 / 8;
- classes[i + pos] =
- merge_classes (subclasses[i], classes[i + pos]);
- }
- }
- }
- break;
- case TYPE_CODE_ARRAY:
- {
- int num;
-
- num = classify_argument (TYPE_TARGET_TYPE (type),
- subclasses, bit_offset);
- if (!num)
- return 0;
-
- /* The partial classes are now full classes. */
- if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
- subclasses[0] = X86_64_SSE_CLASS;
- if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
- subclasses[0] = X86_64_INTEGER_CLASS;
-
- for (i = 0; i < words; i++)
- classes[i] = subclasses[i % num];
- }
- break;
- case TYPE_CODE_UNION:
- {
- int j;
- {
- for (j = 0; j < TYPE_NFIELDS (type); ++j)
- {
- int num;
- num = classify_argument (TYPE_FIELDS (type)[j].type,
- subclasses, bit_offset);
- if (!num)
- return 0;
- for (i = 0; i < num; i++)
- classes[i] = merge_classes (subclasses[i], classes[i]);
- }
- }
- }
- break;
- default:
- break;
- }
- /* Final merger cleanup. */
- for (i = 0; i < words; i++)
- {
- /* If one class is MEMORY, everything should be passed in
- memory. */
- if (classes[i] == X86_64_MEMORY_CLASS)
- return 0;
-
- /* The X86_64_SSEUP_CLASS should be always preceeded by
- X86_64_SSE_CLASS. */
- if (classes[i] == X86_64_SSEUP_CLASS
- && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
- classes[i] = X86_64_SSE_CLASS;
-
- /* X86_64_X87UP_CLASS should be preceeded by X86_64_X87_CLASS. */
- if (classes[i] == X86_64_X87UP_CLASS
- && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
- classes[i] = X86_64_SSE_CLASS;
- }
- return words;
- }
- break;
- case TYPE_CODE_FLT:
- switch (bytes)
- {
- case 4:
- if (!(bit_offset % 64))
- classes[0] = X86_64_SSESF_CLASS;
- else
- classes[0] = X86_64_SSE_CLASS;
- return 1;
- case 8:
- classes[0] = X86_64_SSEDF_CLASS;
- return 1;
- case 16:
- classes[0] = X86_64_X87_CLASS;
- classes[1] = X86_64_X87UP_CLASS;
- return 2;
- }
- break;
- case TYPE_CODE_ENUM:
- case TYPE_CODE_REF:
- case TYPE_CODE_INT:
- case TYPE_CODE_PTR:
- switch (bytes)
- {
- case 1:
- case 2:
- case 4:
- case 8:
- if (bytes * 8 + bit_offset <= 32)
- classes[0] = X86_64_INTEGERSI_CLASS;
- else
- classes[0] = X86_64_INTEGER_CLASS;
- return 1;
- case 16:
- classes[0] = classes[1] = X86_64_INTEGER_CLASS;
- return 2;
- default:
- break;
- }
- case TYPE_CODE_VOID:
- return 0;
- default: /* Avoid warning. */
- break;
- }
- internal_error (__FILE__, __LINE__,
- "classify_argument: unknown argument type");
-}
-
-/* Examine the argument and set *INT_NREGS and *SSE_NREGS to the
- number of registers required based on the information passed in
- CLASSES. Return 0 if parameter should be passed in memory. */
-
-static int
-examine_argument (enum x86_64_reg_class classes[MAX_CLASSES],
- int n, int *int_nregs, int *sse_nregs)
-{
- *int_nregs = 0;
- *sse_nregs = 0;
- if (!n)
- return 0;
- for (n--; n >= 0; n--)
- switch (classes[n])
- {
- case X86_64_INTEGER_CLASS:
- case X86_64_INTEGERSI_CLASS:
- (*int_nregs)++;
- break;
- case X86_64_SSE_CLASS:
- case X86_64_SSESF_CLASS:
- case X86_64_SSEDF_CLASS:
- (*sse_nregs)++;
- break;
- case X86_64_NO_CLASS:
- case X86_64_SSEUP_CLASS:
- case X86_64_X87_CLASS:
- case X86_64_X87UP_CLASS:
- break;
- case X86_64_MEMORY_CLASS:
- internal_error (__FILE__, __LINE__,
- "examine_argument: unexpected memory class");
- }
- return 1;
-}
-
-#define INT_REGS 6
-#define SSE_REGS 8
-
-static CORE_ADDR
-x86_64_push_arguments (struct regcache *regcache, int nargs,
- struct value **args, CORE_ADDR sp)
-{
- int intreg = 0;
- int ssereg = 0;
- /* For varargs functions we have to pass the total number of SSE
- registers used in %rax. So, let's count this number. */
- int total_sse_args = 0;
- /* Once an SSE/int argument is passed on the stack, all subsequent
- arguments are passed there. */
- int sse_stack = 0;
- int int_stack = 0;
- unsigned total_sp;
- int i;
- char buf[8];
- static int int_parameter_registers[INT_REGS] =
- {
- X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */
- X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */
- 8, 9 /* %r8, %r9 */
- };
- /* %xmm0 - %xmm7 */
- static int sse_parameter_registers[SSE_REGS] =
- {
- X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
- X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
- X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
- X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
- };
- int stack_values_count = 0;
- int *stack_values;
- stack_values = alloca (nargs * sizeof (int));
-
- for (i = 0; i < nargs; i++)
- {
- enum x86_64_reg_class class[MAX_CLASSES];
- int n = classify_argument (args[i]->type, class, 0);
- int needed_intregs;
- int needed_sseregs;
-
- if (!n ||
- !examine_argument (class, n, &needed_intregs, &needed_sseregs))
- { /* memory class */
- stack_values[stack_values_count++] = i;
- }
- else
- {
- int j;
- int offset = 0;
-
- if (intreg / 2 + needed_intregs > INT_REGS)
- int_stack = 1;
- if (ssereg / 2 + needed_sseregs > SSE_REGS)
- sse_stack = 1;
- if (!sse_stack)
- total_sse_args += needed_sseregs;
-
- for (j = 0; j < n; j++)
- {
- switch (class[j])
- {
- case X86_64_NO_CLASS:
- break;
- case X86_64_INTEGER_CLASS:
- if (int_stack)
- stack_values[stack_values_count++] = i;
- else
- {
- regcache_cooked_write
- (regcache, int_parameter_registers[(intreg + 1) / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- intreg += 2;
- }
- break;
- case X86_64_INTEGERSI_CLASS:
- if (int_stack)
- stack_values[stack_values_count++] = i;
- else
- {
- LONGEST val = extract_signed_integer
- (VALUE_CONTENTS_ALL (args[i]) + offset, 4);
- regcache_cooked_write_signed
- (regcache, int_parameter_registers[intreg / 2], val);
-
- offset += 8;
- intreg++;
- }
- break;
- case X86_64_SSEDF_CLASS:
- case X86_64_SSESF_CLASS:
- case X86_64_SSE_CLASS:
- if (sse_stack)
- stack_values[stack_values_count++] = i;
- else
- {
- regcache_cooked_write
- (regcache, sse_parameter_registers[(ssereg + 1) / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- ssereg += 2;
- }
- break;
- case X86_64_SSEUP_CLASS:
- if (sse_stack)
- stack_values[stack_values_count++] = i;
- else
- {
- regcache_cooked_write
- (regcache, sse_parameter_registers[ssereg / 2],
- VALUE_CONTENTS_ALL (args[i]) + offset);
- offset += 8;
- ssereg++;
- }
- break;
- case X86_64_X87_CLASS:
- case X86_64_MEMORY_CLASS:
- stack_values[stack_values_count++] = i;
- break;
- case X86_64_X87UP_CLASS:
- break;
- default:
- internal_error (__FILE__, __LINE__,
- "Unexpected argument class");
- }
- intreg += intreg % 2;
- ssereg += ssereg % 2;
- }
- }
- }
-
- /* We have to make sure that the stack is 16-byte aligned after the
- setup. Let's calculate size of arguments first, align stack and
- then fill in the arguments. */
- total_sp = 0;
- for (i = 0; i < stack_values_count; i++)
- {
- struct value *arg = args[stack_values[i]];
- int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
- total_sp += (len + 7) & ~7;
- }
- /* total_sp is now a multiple of 8, if it is not a multiple of 16,
- change the stack pointer so that it will be afterwards correctly
- aligned. */
- if (total_sp & 15)
- sp -= 8;
-
- /* Push any remaining arguments onto the stack. */
- while (--stack_values_count >= 0)
- {
- struct value *arg = args[stack_values[stack_values_count]];
- int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
-
- /* Make sure the stack is 8-byte-aligned. */
- sp -= (len + 7) & ~7;
- write_memory (sp, VALUE_CONTENTS_ALL (arg), len);
- }
-
- /* Write number of SSE type arguments to RAX to take care of varargs
- functions. */
- store_unsigned_integer (buf, 8, total_sse_args);
- regcache_cooked_write (regcache, X86_64_RAX_REGNUM, buf);
-
- return sp;
-}
-
/* Register classes as defined in the psABI. */
enum amd64_reg_class
static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
+/* Return non-zero if TYPE is a non-POD structure or union type. */
+
+static int
+amd64_non_pod_p (struct type *type)
+{
+ /* ??? A class with a base class certainly isn't POD, but does this
+ catch all non-POD structure types? */
+ if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
+ return 1;
+
+ return 0;
+}
+
/* Classify TYPE according to the rules for aggregate (structures and
arrays) and union types, and store the result in CLASS. */
/* 1. If the size of an object is larger than two eightbytes, or in
C++, is a non-POD structure or union type, or contains
unaligned fields, it has class memory. */
- if (len > 16)
+ if (len > 16 || amd64_non_pod_p (type))
{
class[0] = class[1] = AMD64_MEMORY;
return;
int pos = TYPE_FIELD_BITPOS (type, i) / 64;
enum amd64_reg_class subclass[2];
+ /* Ignore static fields. */
+ if (TYPE_FIELD_STATIC (type, i))
+ continue;
+
gdb_assert (pos == 0 || pos == 1);
amd64_classify (subtype, subclass);
\f
static CORE_ADDR
-x86_64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
- struct regcache *regcache, CORE_ADDR bp_addr,
- int nargs, struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
+amd64_push_arguments (struct regcache *regcache, int nargs,
+ struct value **args, CORE_ADDR sp, int struct_return)
+{
+ static int integer_regnum[] =
+ {
+ X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */
+ X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */
+ 8, 9 /* %r8, %r9 */
+ };
+ static int sse_regnum[] =
+ {
+ /* %xmm0 ... %xmm7 */
+ X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
+ X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
+ X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
+ X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
+ };
+ struct value **stack_args = alloca (nargs * sizeof (struct value *));
+ int num_stack_args = 0;
+ int num_elements = 0;
+ int element = 0;
+ int integer_reg = 0;
+ int sse_reg = 0;
+ int i;
+
+ /* Reserve a register for the "hidden" argument. */
+ if (struct_return)
+ integer_reg++;
+
+ for (i = 0; i < nargs; i++)
+ {
+ struct type *type = VALUE_TYPE (args[i]);
+ int len = TYPE_LENGTH (type);
+ enum amd64_reg_class class[2];
+ int needed_integer_regs = 0;
+ int needed_sse_regs = 0;
+ int j;
+
+ /* Classify argument. */
+ amd64_classify (type, class);
+
+ /* Calculate the number of integer and SSE registers needed for
+ this argument. */
+ for (j = 0; j < 2; j++)
+ {
+ if (class[j] == AMD64_INTEGER)
+ needed_integer_regs++;
+ else if (class[j] == AMD64_SSE)
+ needed_sse_regs++;
+ }
+
+ /* Check whether enough registers are available, and if the
+ argument should be passed in registers at all. */
+ if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
+ || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
+ || (needed_integer_regs == 0 && needed_sse_regs == 0))
+ {
+ /* The argument will be passed on the stack. */
+ num_elements += ((len + 7) / 8);
+ stack_args[num_stack_args++] = args[i];
+ }
+ else
+ {
+ /* The argument will be passed in registers. */
+ char *valbuf = VALUE_CONTENTS (args[i]);
+ char buf[8];
+
+ gdb_assert (len <= 16);
+
+ for (j = 0; len > 0; j++, len -= 8)
+ {
+ int regnum = -1;
+ int offset = 0;
+
+ switch (class[j])
+ {
+ case AMD64_INTEGER:
+ regnum = integer_regnum[integer_reg++];
+ break;
+
+ case AMD64_SSE:
+ regnum = sse_regnum[sse_reg++];
+ break;
+
+ case AMD64_SSEUP:
+ gdb_assert (sse_reg > 0);
+ regnum = sse_regnum[sse_reg - 1];
+ offset = 8;
+ break;
+
+ default:
+ gdb_assert (!"Unexpected register class.");
+ }
+
+ gdb_assert (regnum != -1);
+ memset (buf, 0, sizeof buf);
+ memcpy (buf, valbuf + j * 8, min (len, 8));
+ regcache_raw_write_part (regcache, regnum, offset, 8, buf);
+ }
+ }
+ }
+
+ /* Allocate space for the arguments on the stack. */
+ sp -= num_elements * 8;
+
+ /* The psABI says that "The end of the input argument area shall be
+ aligned on a 16 byte boundary." */
+ sp &= ~0xf;
+
+ /* Write out the arguments to the stack. */
+ for (i = 0; i < num_stack_args; i++)
+ {
+ struct type *type = VALUE_TYPE (stack_args[i]);
+ char *valbuf = VALUE_CONTENTS (stack_args[i]);
+ int len = TYPE_LENGTH (type);
+
+ write_memory (sp + element * 8, valbuf, len);
+ element += ((len + 7) / 8);
+ }
+
+ /* The psABI says that "For calls that may call functions that use
+ varargs or stdargs (prototype-less calls or calls to functions
+ containing ellipsis (...) in the declaration) %al is used as
+ hidden argument to specify the number of SSE registers used. */
+ regcache_raw_write_unsigned (regcache, X86_64_RAX_REGNUM, sse_reg);
+ return sp;
+}
+
+static CORE_ADDR
+amd64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
{
char buf[8];
/* Pass arguments. */
- sp = x86_64_push_arguments (regcache, nargs, args, sp);
+ sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
/* Pass "hidden" argument". */
if (struct_return)
\f
/* The maximum number of saved registers. This should include %rip. */
-#define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS
+#define AMD64_NUM_SAVED_REGS X86_64_NUM_GREGS
-struct x86_64_frame_cache
+struct amd64_frame_cache
{
/* Base address. */
CORE_ADDR base;
CORE_ADDR pc;
/* Saved registers. */
- CORE_ADDR saved_regs[X86_64_NUM_SAVED_REGS];
+ CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
CORE_ADDR saved_sp;
/* Do we have a frame? */
/* Allocate and initialize a frame cache. */
-static struct x86_64_frame_cache *
-x86_64_alloc_frame_cache (void)
+static struct amd64_frame_cache *
+amd64_alloc_frame_cache (void)
{
- struct x86_64_frame_cache *cache;
+ struct amd64_frame_cache *cache;
int i;
- cache = FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache);
+ cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
/* Base address. */
cache->base = 0;
/* Saved registers. We initialize these to -1 since zero is a valid
offset (that's where %rbp is supposed to be stored). */
- for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
+ for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
cache->saved_regs[i] = -1;
cache->saved_sp = 0;
to have no prologue and thus no valid frame pointer in %rbp. */
static CORE_ADDR
-x86_64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
- struct x86_64_frame_cache *cache)
+amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
+ struct amd64_frame_cache *cache)
{
static unsigned char proto[3] = { 0x48, 0x89, 0xe5 };
unsigned char buf[3];
/* Return PC of first real instruction. */
static CORE_ADDR
-x86_64_skip_prologue (CORE_ADDR start_pc)
+amd64_skip_prologue (CORE_ADDR start_pc)
{
- struct x86_64_frame_cache cache;
+ struct amd64_frame_cache cache;
CORE_ADDR pc;
- pc = x86_64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache);
+ pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache);
if (cache.frameless_p)
return start_pc;
/* Normal frames. */
-static struct x86_64_frame_cache *
-x86_64_frame_cache (struct frame_info *next_frame, void **this_cache)
+static struct amd64_frame_cache *
+amd64_frame_cache (struct frame_info *next_frame, void **this_cache)
{
- struct x86_64_frame_cache *cache;
+ struct amd64_frame_cache *cache;
char buf[8];
int i;
if (*this_cache)
return *this_cache;
- cache = x86_64_alloc_frame_cache ();
+ cache = amd64_alloc_frame_cache ();
*this_cache = cache;
cache->pc = frame_func_unwind (next_frame);
if (cache->pc != 0)
- x86_64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
+ amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
if (cache->frameless_p)
{
/* Adjust all the saved registers such that they contain addresses
instead of offsets. */
- for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
+ for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
if (cache->saved_regs[i] != -1)
cache->saved_regs[i] += cache->base;
}
static void
-x86_64_frame_this_id (struct frame_info *next_frame, void **this_cache,
- struct frame_id *this_id)
+amd64_frame_this_id (struct frame_info *next_frame, void **this_cache,
+ struct frame_id *this_id)
{
- struct x86_64_frame_cache *cache =
- x86_64_frame_cache (next_frame, this_cache);
+ struct amd64_frame_cache *cache =
+ amd64_frame_cache (next_frame, this_cache);
/* This marks the outermost frame. */
if (cache->base == 0)
}
static void
-x86_64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
- int regnum, int *optimizedp,
- enum lval_type *lvalp, CORE_ADDR *addrp,
- int *realnump, void *valuep)
+amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
+ int regnum, int *optimizedp,
+ enum lval_type *lvalp, CORE_ADDR *addrp,
+ int *realnump, void *valuep)
{
- struct x86_64_frame_cache *cache =
- x86_64_frame_cache (next_frame, this_cache);
+ struct amd64_frame_cache *cache =
+ amd64_frame_cache (next_frame, this_cache);
gdb_assert (regnum >= 0);
return;
}
- if (regnum < X86_64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
+ if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
{
*optimizedp = 0;
*lvalp = lval_memory;
optimizedp, lvalp, addrp, realnump, valuep);
}
-static const struct frame_unwind x86_64_frame_unwind =
+static const struct frame_unwind amd64_frame_unwind =
{
NORMAL_FRAME,
- x86_64_frame_this_id,
- x86_64_frame_prev_register
+ amd64_frame_this_id,
+ amd64_frame_prev_register
};
static const struct frame_unwind *
-x86_64_frame_sniffer (struct frame_info *next_frame)
+amd64_frame_sniffer (struct frame_info *next_frame)
{
- return &x86_64_frame_unwind;
+ return &amd64_frame_unwind;
}
\f
64-bit variants. This would require using identical frame caches
on both platforms. */
-static struct x86_64_frame_cache *
-x86_64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
+static struct amd64_frame_cache *
+amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
{
- struct x86_64_frame_cache *cache;
+ struct amd64_frame_cache *cache;
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
CORE_ADDR addr;
char buf[8];
if (*this_cache)
return *this_cache;
- cache = x86_64_alloc_frame_cache ();
+ cache = amd64_alloc_frame_cache ();
frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 8) - 8;
addr = tdep->sigcontext_addr (next_frame);
gdb_assert (tdep->sc_reg_offset);
- gdb_assert (tdep->sc_num_regs <= X86_64_NUM_SAVED_REGS);
+ gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
for (i = 0; i < tdep->sc_num_regs; i++)
if (tdep->sc_reg_offset[i] != -1)
cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
}
static void
-x86_64_sigtramp_frame_this_id (struct frame_info *next_frame,
- void **this_cache, struct frame_id *this_id)
+amd64_sigtramp_frame_this_id (struct frame_info *next_frame,
+ void **this_cache, struct frame_id *this_id)
{
- struct x86_64_frame_cache *cache =
- x86_64_sigtramp_frame_cache (next_frame, this_cache);
+ struct amd64_frame_cache *cache =
+ amd64_sigtramp_frame_cache (next_frame, this_cache);
(*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
}
static void
-x86_64_sigtramp_frame_prev_register (struct frame_info *next_frame,
- void **this_cache,
- int regnum, int *optimizedp,
- enum lval_type *lvalp, CORE_ADDR *addrp,
- int *realnump, void *valuep)
+amd64_sigtramp_frame_prev_register (struct frame_info *next_frame,
+ void **this_cache,
+ int regnum, int *optimizedp,
+ enum lval_type *lvalp, CORE_ADDR *addrp,
+ int *realnump, void *valuep)
{
/* Make sure we've initialized the cache. */
- x86_64_sigtramp_frame_cache (next_frame, this_cache);
+ amd64_sigtramp_frame_cache (next_frame, this_cache);
- x86_64_frame_prev_register (next_frame, this_cache, regnum,
- optimizedp, lvalp, addrp, realnump, valuep);
+ amd64_frame_prev_register (next_frame, this_cache, regnum,
+ optimizedp, lvalp, addrp, realnump, valuep);
}
-static const struct frame_unwind x86_64_sigtramp_frame_unwind =
+static const struct frame_unwind amd64_sigtramp_frame_unwind =
{
SIGTRAMP_FRAME,
- x86_64_sigtramp_frame_this_id,
- x86_64_sigtramp_frame_prev_register
+ amd64_sigtramp_frame_this_id,
+ amd64_sigtramp_frame_prev_register
};
static const struct frame_unwind *
-x86_64_sigtramp_frame_sniffer (struct frame_info *next_frame)
+amd64_sigtramp_frame_sniffer (struct frame_info *next_frame)
{
CORE_ADDR pc = frame_pc_unwind (next_frame);
char *name;
{
gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr);
- return &x86_64_sigtramp_frame_unwind;
+ return &amd64_sigtramp_frame_unwind;
}
return NULL;
\f
static CORE_ADDR
-x86_64_frame_base_address (struct frame_info *next_frame, void **this_cache)
+amd64_frame_base_address (struct frame_info *next_frame, void **this_cache)
{
- struct x86_64_frame_cache *cache =
- x86_64_frame_cache (next_frame, this_cache);
+ struct amd64_frame_cache *cache =
+ amd64_frame_cache (next_frame, this_cache);
return cache->base;
}
-static const struct frame_base x86_64_frame_base =
+static const struct frame_base amd64_frame_base =
{
- &x86_64_frame_unwind,
- x86_64_frame_base_address,
- x86_64_frame_base_address,
- x86_64_frame_base_address
+ &amd64_frame_unwind,
+ amd64_frame_base_address,
+ amd64_frame_base_address,
+ amd64_frame_base_address
};
static struct frame_id
-x86_64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
+amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
char buf[8];
CORE_ADDR fp;
/* 16 byte align the SP per frame requirements. */
static CORE_ADDR
-x86_64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
+amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
{
return sp & -(CORE_ADDR)16;
}
registers in REGSET. */
static void
-x86_64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
- int regnum, const void *fpregs, size_t len)
+amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *fpregs, size_t len)
{
const struct gdbarch_tdep *tdep = regset->descr;
by SECT_NAME and SECT_SIZE. */
static const struct regset *
-x86_64_regset_from_core_section (struct gdbarch *gdbarch,
- const char *sect_name, size_t sect_size)
+amd64_regset_from_core_section (struct gdbarch *gdbarch,
+ const char *sect_name, size_t sect_size)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
{
tdep->fpregset = XMALLOC (struct regset);
tdep->fpregset->descr = tdep;
- tdep->fpregset->supply_regset = x86_64_supply_fpregset;
+ tdep->fpregset->supply_regset = amd64_supply_fpregset;
}
return tdep->fpregset;
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
- /* In contrast to the i386, on the x86-64 a `long double' actually
- takes up 128 bits, even though it's still based on the i387
- extended floating-point format which has only 80 significant bits. */
+ /* In contrast to the i386, on AMD64 a `long double' actually takes
+ up 128 bits, even though it's still based on the i387 extended
+ floating-point format which has only 80 significant bits. */
set_gdbarch_long_double_bit (gdbarch, 128);
- set_gdbarch_num_regs (gdbarch, X86_64_NUM_REGS);
- set_gdbarch_register_name (gdbarch, x86_64_register_name);
- set_gdbarch_register_type (gdbarch, x86_64_register_type);
+ set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
+ set_gdbarch_register_name (gdbarch, amd64_register_name);
+ set_gdbarch_register_type (gdbarch, amd64_register_type);
/* Register numbers of various important registers. */
set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */
set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */
set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */
- /* The "default" register numbering scheme for the x86-64 is
- referred to as the "DWARF Register Number Mapping" in the System
- V psABI. The preferred debugging format for all known x86-64
- targets is actually DWARF2, and GCC doesn't seem to support DWARF
- (that is DWARF-1), but we provide the same mapping just in case.
- This mapping is also used for stabs, which GCC does support. */
- set_gdbarch_stab_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
- set_gdbarch_dwarf_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
- set_gdbarch_dwarf2_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
+ /* The "default" register numbering scheme for AMD64 is referred to
+ as the "DWARF Register Number Mapping" in the System V psABI.
+ The preferred debugging format for all known AMD64 targets is
+ actually DWARF2, and GCC doesn't seem to support DWARF (that is
+ DWARF-1), but we provide the same mapping just in case. This
+ mapping is also used for stabs, which GCC does support. */
+ set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
+ set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
/* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
- be in use on any of the supported x86-64 targets. */
+ be in use on any of the supported AMD64 targets. */
/* Call dummy code. */
- set_gdbarch_push_dummy_call (gdbarch, x86_64_push_dummy_call);
- set_gdbarch_frame_align (gdbarch, x86_64_frame_align);
+ set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
+ set_gdbarch_frame_align (gdbarch, amd64_frame_align);
set_gdbarch_frame_red_zone_size (gdbarch, 128);
- set_gdbarch_convert_register_p (gdbarch, x86_64_convert_register_p);
+ set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p);
set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
set_gdbarch_return_value (gdbarch, amd64_return_value);
- /* Override, since this is handled by x86_64_extract_return_value. */
- set_gdbarch_extract_struct_value_address (gdbarch, NULL);
- set_gdbarch_skip_prologue (gdbarch, x86_64_skip_prologue);
+ set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
/* Avoid wiring in the MMX registers for now. */
set_gdbarch_num_pseudo_regs (gdbarch, 0);
tdep->mm0_regnum = -1;
- set_gdbarch_unwind_dummy_id (gdbarch, x86_64_unwind_dummy_id);
+ set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
/* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
- since all supported x86-64 targets are ELF, but that might change
+ since all supported AMD64 targets are ELF, but that might change
in the future. */
set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section);
- frame_unwind_append_sniffer (gdbarch, x86_64_sigtramp_frame_sniffer);
- frame_unwind_append_sniffer (gdbarch, x86_64_frame_sniffer);
- frame_base_set_default (gdbarch, &x86_64_frame_base);
+ frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
+ frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
+ frame_base_set_default (gdbarch, &amd64_frame_base);
/* If we have a register mapping, enable the generic core file support. */
if (tdep->gregset_reg_offset)
set_gdbarch_regset_from_core_section (gdbarch,
- x86_64_regset_from_core_section);
+ amd64_regset_from_core_section);
}
\f
projects / deliverable / binutils-gdb.git / blobdiff