static int
extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int winsize = 4;
int insn;
gdb_byte buf[4];
/* Read the previous instruction (should be a call[x]{4|8|12}. */
read_memory (pc-3, buf, 3);
- insn = extract_unsigned_integer (buf, 3);
+ insn = extract_unsigned_integer (buf, 3, byte_order);
/* Decode call instruction:
Little Endian
call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
- if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
+ if (byte_order == BFD_ENDIAN_LITTLE)
{
if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
int regnum,
gdb_byte *buffer)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+
DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
regnum, xtensa_register_name (gdbarch, regnum));
regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
regnum = arreg_number (gdbarch, regnum,
- extract_unsigned_integer (buf, 4));
+ extract_unsigned_integer (buf, 4, byte_order));
}
/* We can always read non-pseudo registers. */
int regnum,
const gdb_byte *buffer)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+
DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
regnum, xtensa_register_name (gdbarch, regnum));
regcache_raw_read (regcache,
gdbarch_tdep (gdbarch)->wb_regnum, buf);
regnum = arreg_number (gdbarch, regnum,
- extract_unsigned_integer (buf, 4));
+ extract_unsigned_integer (buf, 4, byte_order));
}
/* We can always write 'core' registers.
xtensa_frame_cache_t *cache;
CORE_ADDR ra, wb, ws, pc, sp, ps;
struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
unsigned int fp_regnum;
char op1;
int windowed;
ws = get_frame_register_unsigned (this_frame,
gdbarch_tdep (gdbarch)->ws_regnum);
- op1 = read_memory_integer (pc, 1);
+ op1 = read_memory_integer (pc, 1, byte_order);
if (XTENSA_IS_ENTRY (gdbarch, op1))
{
int callinc = CALLINC (ps);
/* Set A4...A7/A11. */
/* Get the SP of the frame previous to the previous one.
To achieve this, we have to dereference SP twice. */
- sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
- sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
+ sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
+ sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
sp -= cache->wd.callsize * 4;
for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
We can read caller's SP from the proper spill loction. */
sp = get_frame_register_unsigned
(this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
- cache->prev_sp = read_memory_integer (sp - 12, 4);
+ cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
}
else
{
int struct_return,
CORE_ADDR struct_addr)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int i;
int size, onstack_size;
gdb_byte *buf = (gdb_byte *) alloca (16);
if (struct_return)
{
- store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
+ store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
}
than REGISTER_SIZE; for larger odd-sized structures the excess
will be left-aligned in the register on both endiannesses. */
- if (n < REGISTER_SIZE
- && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
{
- ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
+ ULONGEST v;
+ v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
- store_unsigned_integer (buf, REGISTER_SIZE, v);
+ store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
regcache_cooked_write (regcache, r, buf);
cp += REGISTER_SIZE;
{
ra = (bp_addr & 0x3fffffff) | 0x40000000;
regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
- ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
+ ps = extract_unsigned_integer (buf, 4, byte_order) & ~0x00030000;
regcache_cooked_write_unsigned
(regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
regcache_cooked_write_unsigned (regcache,
is only one register window corresponding to WINDOWEBASE. */
regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
- regcache_cooked_write_unsigned (regcache,
- gdbarch_tdep (gdbarch)->ws_regnum,
- 1 << extract_unsigned_integer (buf, 4));
+ regcache_cooked_write_unsigned
+ (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
+ 1 << extract_unsigned_integer (buf, 4, byte_order));
}
else
{
the stack frame. */
static void
-call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
+call0_track_op (struct gdbarch *gdbarch,
+ xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
xtensa_insn_kind opclass, int nods, unsigned odv[],
CORE_ADDR pc, CORE_ADDR litbase, int spreg)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
unsigned litaddr, litval;
switch (opclass)
litaddr = litbase & 1
? (litbase & ~1) + (signed)odv[1]
: (pc + 3 + (signed)odv[1]) & ~3;
- litval = read_memory_integer(litaddr, 4);
+ litval = read_memory_integer (litaddr, 4, byte_order);
dst[odv[0]].fr_reg = C0_CONST;
dst[odv[0]].fr_ofs = litval;
break;
because they begin with default assumptions that analysis may change. */
static CORE_ADDR
-call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
+call0_analyze_prologue (struct gdbarch *gdbarch,
+ CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
int nregs, xtensa_c0reg_t rt[], int *call0)
{
CORE_ADDR ia; /* Current insn address in prologue. */
}
/* Track register movement and modification for this operation. */
- call0_track_op (rt, rtmp, opclass, nods, odv, ia, litbase, 1);
+ call0_track_op (gdbarch, rt, rtmp, opclass,
+ nods, odv, ia, litbase, 1);
}
}
done:
xtensa_frame_cache_t *cache, CORE_ADDR pc, CORE_ADDR litbase)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR start_pc; /* The beginning of the function. */
CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
CORE_ADDR sp, fp, ra;
if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
{
- body_pc = call0_analyze_prologue (start_pc, pc, litbase, C0_NREGS,
+ body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, litbase,
+ C0_NREGS,
&cache->c0.c0_rt[0],
&cache->call0);
}
to_stk = cache->c0.c0_rt[C0_RA].to_stk;
if (to_stk != C0_NOSTK)
ra = (CORE_ADDR)
- read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
+ read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
+ 4, byte_order);
else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
&& cache->c0.c0_rt[C0_RA].fr_ofs == 0)
}
/* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
- body_pc = call0_analyze_prologue(start_pc, 0, 0, 0, NULL, NULL);
+ body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 0, NULL, NULL);
return body_pc != 0 ? body_pc : start_pc;
}
projects / deliverable / binutils-gdb.git / blobdiff