/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
- Copyright (C) 2003-2015 Free Software Foundation, Inc.
+ Copyright (C) 2003-2016 Free Software Foundation, Inc.
This file is part of GDB.
/* For xtensa-config.c to expand to the structure above. */
#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
- {#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \
+ {#name, ofs, (xtensa_register_type_t) (ty), \
+ ((xtensa_register_group_t) \
+ ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2)))), \
ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
-#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
+#define XTREG_END \
+ {0, 0, (xtensa_register_type_t) 0, (xtensa_register_group_t) 0, \
+ 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
.spill_location = -1, \
.spill_size = (spillsz), \
.unused = 0, \
- .call_abi = CallAbiDefault, \
+ .call_abi = (XSHAL_ABI == XTHAL_ABI_CALL0 \
+ ? CallAbiCall0Only \
+ : CallAbiDefault), \
.debug_interrupt_level = XCHAL_DEBUGLEVEL, \
.icache_line_bytes = XCHAL_ICACHE_LINESIZE, \
.dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \