Support 64-bit entry size in SHT_HASH (for s390).

[deliverable/binutils-gdb.git] / gold / arm.cc

diff --git a/gold/arm.cc b/gold/arm.cc
index be2294c3e1baedbb00ecb4269e55e30c0263a771..2795c943c644ae4cf06ed2ed05ffd224215a6da4 100644 (file)
--- a/gold/arm.cc
+++ b/gold/arm.cc
@@ -2997,7 +2997,8 @@ const Target::Target_info Target_arm<big_endian>::arm_info =
   0,                   // large_common_section_flags
   ".ARM.attributes",   // attributes_section
   "aeabi",             // attributes_vendor
-  "_start"             // entry_symbol_name
+  "_start",            // entry_symbol_name
+  32,                  // hash_entry_size
 };
 
 // Arm relocate functions class
@@ -4542,7 +4543,7 @@ Reloc_stub::stub_type_for_reloc(
   // This is a bit ugly but we want to avoid using a templated class for
   // big and little endianities.
   bool may_use_blx;
-  bool should_force_pic_veneer;
+  bool should_force_pic_veneer = parameters->options().pic_veneer();
   bool thumb2;
   bool thumb_only;
   if (parameters->target().is_big_endian())
@@ -4550,7 +4551,7 @@ Reloc_stub::stub_type_for_reloc(
       const Target_arm<true>* big_endian_target =
        Target_arm<true>::default_target();
       may_use_blx = big_endian_target->may_use_v5t_interworking();
-      should_force_pic_veneer = big_endian_target->should_force_pic_veneer();
+      should_force_pic_veneer |= big_endian_target->should_force_pic_veneer();
       thumb2 = big_endian_target->using_thumb2();
       thumb_only = big_endian_target->using_thumb_only();
     }
@@ -4559,7 +4560,8 @@ Reloc_stub::stub_type_for_reloc(
       const Target_arm<false>* little_endian_target =
        Target_arm<false>::default_target();
       may_use_blx = little_endian_target->may_use_v5t_interworking();
-      should_force_pic_veneer = little_endian_target->should_force_pic_veneer();
+      should_force_pic_veneer |=
+        little_endian_target->should_force_pic_veneer();
       thumb2 = little_endian_target->using_thumb2();
       thumb_only = little_endian_target->using_thumb_only();
     }
@@ -6255,16 +6257,9 @@ Arm_relobj<big_endian>::scan_section_for_cortex_a8_erratum(
     this->mapping_symbols_info_.lower_bound(section_start);
 
   // There are no mapping symbols for this section.  Treat it as a data-only
-  // section.  Issue a warning if section is marked as containing
-  // instructions.
+  // section.
   if (p == this->mapping_symbols_info_.end() || p->first.first != shndx)
-    {
-      if ((this->section_flags(shndx) & elfcpp::SHF_EXECINSTR) != 0)
-       gold_warning(_("cannot scan executable section %u of %s for Cortex-A8 "
-                      "erratum because it has no mapping symbols."),
-                    shndx, this->name().c_str());
-      return;
-    }
+    return;
 
   Arm_address output_address =
     this->simple_input_section_output_address(shndx, os);
@@ -7938,6 +7933,13 @@ Target_arm<big_endian>::make_plt_section(
                                      (elfcpp::SHF_ALLOC
                                       | elfcpp::SHF_EXECINSTR),
                                      this->plt_, ORDER_PLT, false);
+      symtab->define_in_output_data("$a", NULL,
+                                   Symbol_table::PREDEFINED,
+                                   this->plt_,
+                                   0, 0, elfcpp::STT_NOTYPE,
+                                   elfcpp::STB_LOCAL,
+                                   elfcpp::STV_DEFAULT, 0,
+                                   false, false);
     }
 }
 
@@ -10556,6 +10558,7 @@ Target_arm<big_endian>::do_adjust_elf_header(
   }
   elfcpp::Ehdr_write<32, big_endian> oehdr(view);
   oehdr.put_e_ident(e_ident);
+  oehdr.put_e_flags(this->processor_specific_flags());
 }
 
 // do_make_elf_object to override the same function in the base class.
@@ -10752,6 +10755,24 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
       T(V7E_M),        // V6S_M.
       T(V7E_M) // V7E_M.
     };
+  static const int v8[] =
+    {
+      T(V8),   // PRE_V4.
+      T(V8),   // V4.
+      T(V8),   // V4T.
+      T(V8),   // V5T.
+      T(V8),   // V5TE.
+      T(V8),   // V5TEJ.
+      T(V8),   // V6.
+      T(V8),   // V6KZ.
+      T(V8),   // V6T2.
+      T(V8),   // V6K.
+      T(V8),   // V7.
+      T(V8),   // V6_M.
+      T(V8),   // V6S_M.
+      T(V8),   // V7E_M.
+      T(V8)    // V8.
+    };
   static const int v4t_plus_v6_m[] =
     {
       -1,              // PRE_V4.
@@ -10768,6 +10789,7 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
       T(V6_M),         // V6_M.
       T(V6S_M),                // V6S_M.
       T(V7E_M),                // V7E_M.
+      T(V8),           // V8.
       T(V4T_PLUS_V6_M) // V4T plus V6_M.
     };
   static const int* comb[] =
@@ -10778,6 +10800,7 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
       v6_m,
       v6s_m,
       v7e_m,
+      v8,
       // Pseudo-architecture.
       v4t_plus_v6_m
     };
@@ -10875,7 +10898,8 @@ Target_arm<big_endian>::tag_cpu_name_value(unsigned int value)
    "ARM v7",
    "ARM v6-M",
    "ARM v6S-M",
-   "ARM v7E-M"
+   "ARM v7E-M",
+   "ARM v8"
  };
  const size_t name_table_size = sizeof(name_table) / sizeof(name_table[0]);
 
@@ -12721,7 +12745,8 @@ const Target::Target_info Target_arm_nacl<big_endian>::arm_nacl_info =
   0,                   // large_common_section_flags
   ".ARM.attributes",   // attributes_section
   "aeabi",             // attributes_vendor
-  "_start"             // entry_symbol_name
+  "_start",            // entry_symbol_name
+  32,                  // hash_entry_size
 };
 
 template<bool big_endian>