[AArch64] Additional SVE instructions
[deliverable/binutils-gdb.git] / include / ChangeLog
index 6a61d61fee1bf2809d6731be3394909dd7b3ee32..44f242c4029a561311c29a3b0a828586c4800a03 100644 (file)
@@ -1,3 +1,103 @@
+2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
+       (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
+       (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
+       (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
+
+2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
+       (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
+
+2017-02-22  Andrew Waterman  <andrew@sifive.com>
+
+       * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
+       (CSR_MCOUNTEREN): Likewise.
+       (scounteren): Declare register.
+       (mcounteren): Likewise.
+
+2017-02-14  Andrew Waterman  <andrew@sifive.com>
+
+       * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
+       (MASK_SFENCE_VMA): Likewise.
+       (sfence_vma): Declare instruction.
+
+2017-02-14  Alan Modra  <amodra@gmail.com>
+
+       PR 21118
+       * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
+       (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
+
+2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+        * opcode/hppa.h: Clarify that file is part of GNU opcodes.
+        * opcode/i860.h: Ditto.
+        * opcode/nios2.h: Ditto.
+        * opcode/nios2r1.h: Ditto.
+        * opcode/nios2r2.h: Ditto.
+        * opcode/pru.h: Ditto.
+
+2017-01-24  Alan Hayward  <alan.hayward@arm.com>
+
+       * elf/common.h (NT_ARM_SVE): Define.
+
+2017-01-04  Jiong Wang  <jiong.wang@arm.com>
+
+       * dwarf2.def: Sync with mainline gcc sources.
+
+       2017-01-04  Richard Earnshaw  <rearnsha@arm.com>
+                   Jiong Wang  <jiong.wang@arm.com>
+
+       * dwarf2.def (DW_OP_AARCH64_operation): Reserve the number 0xea.
+       (DW_CFA_GNU_window_save): Comments the multiplexing on AArch64.
+
+2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
+       (AARCH64_ARCH_V8_3): Update.
+
+2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
+
+       * opcode/riscv-opc.h: Add support for the "q" ISA extension.
+
+2017-01-03  Nick Clifton  <nickc@redhat.com>
+
+       * dwarf2.def: Sync with mainline gcc sources
+       * dwarf2.h: Likewise.
+
+       2016-12-21  Jakub Jelinek  <jakub@redhat.com>
+
+       * dwarf2.def (DW_FORM_ref_sup): Renamed to ...
+       (DW_FORM_ref_sup4): ... this.  New form.
+       (DW_FORM_ref_sup8): New form.
+
+       2016-10-17  Jakub Jelinek  <jakub@redhat.com>
+
+       * dwarf2.h (enum dwarf_calling_convention): Add new DWARF5
+       calling convention codes.
+       (enum dwarf_line_number_content_type): New.
+       (enum dwarf_location_list_entry_type): Add DWARF5 DW_LLE_*
+       codes.
+       (enum dwarf_source_language): Add new DWARF5 DW_LANG_* codes.
+       (enum dwarf_macro_record_type): Add DWARF5 DW_MACRO_* codes.
+       (enum dwarf_name_index_attribute): New.
+       (enum dwarf_range_list_entry): New.
+       (enum dwarf_unit_type): New.
+       * dwarf2.def: Add new DWARF5 DW_TAG_*, DW_FORM_*, DW_AT_*,
+       DW_OP_* and DW_ATE_* entries.
+
+       2016-08-15  Jakub Jelinek  <jakub@redhat.com>
+
+       * dwarf2.def (DW_AT_string_length_bit_size,
+       DW_AT_string_length_byte_size): New attributes.
+
+       2016-08-12  Alexandre Oliva <aoliva@redhat.com>
+
+       PR debug/63240
+       * dwarf2.def (DW_AT_deleted, DW_AT_defaulted): New.
+       * dwarf2.h (enum dwarf_defaulted_attribute): New.
+
 2017-01-02  Alan Modra  <amodra@gmail.com>
 
        Update year range in copyright notice of all files.
This page took 0.02486 seconds and 4 git commands to generate.