[AArch64] Additional SVE instructions
[deliverable/binutils-gdb.git] / include / ChangeLog
index b930a730800c5d9a18e0db42ce8522ad9f3ed996..44f242c4029a561311c29a3b0a828586c4800a03 100644 (file)
@@ -1,3 +1,43 @@
+2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
+       (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
+       (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
+       (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
+
+2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
+       (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
+
+2017-02-22  Andrew Waterman  <andrew@sifive.com>
+
+       * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
+       (CSR_MCOUNTEREN): Likewise.
+       (scounteren): Declare register.
+       (mcounteren): Likewise.
+
+2017-02-14  Andrew Waterman  <andrew@sifive.com>
+
+       * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
+       (MASK_SFENCE_VMA): Likewise.
+       (sfence_vma): Declare instruction.
+
+2017-02-14  Alan Modra  <amodra@gmail.com>
+
+       PR 21118
+       * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
+       (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
+
+2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+        * opcode/hppa.h: Clarify that file is part of GNU opcodes.
+        * opcode/i860.h: Ditto.
+        * opcode/nios2.h: Ditto.
+        * opcode/nios2r1.h: Ditto.
+        * opcode/nios2r2.h: Ditto.
+        * opcode/pru.h: Ditto.
+
 2017-01-24  Alan Hayward  <alan.hayward@arm.com>
 
        * elf/common.h (NT_ARM_SVE): Define.
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