Fix an integer overflow in RISC-V relocation handling

[deliverable/binutils-gdb.git] / include / ChangeLog

diff --git a/include/ChangeLog b/include/ChangeLog
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@@ -1,3 +1,105 @@
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+           Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+       * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
+
+2016-12-16  fincs  <fincs.alt1@gmail.com>
+
+       * bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
+
+2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
+       typedef as `elf_internal_abiflags_v0'.
+
+2016-12-13 Renlin Li <renlin.li@arm.com>
+
+       * opcode/aarch64.h (aarch64_operand_class): Remove
+       AARCH64_OPND_CLASS_CP_REG.
+       (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
+       AARCH64_OPND_Cm to AARCH64_OPND_CRm.
+       (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
+
+2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h: Remove references to `>' operand code.
+
+2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
+
+2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h (ASE_DSPR3): Add a comment.
+
+2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
+       (ARM_ARCH_V8_3A): New.
+
+2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
+       instruction classes.
+
+2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
+       hwcaps2.
+
+2016-11-22  Alan Modra  <amodra@gmail.com>
+
+       PR 20744
+       * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
+
+2016-11-03  David Tolnay <dtolnay@gmail.com>
+           Mark Wielaard  <mark@klomp.org>
+
+       * demangle.h (DMGL_RUST): New macro.
+       (DMGL_STYLE_MASK): Add DMGL_RUST.
+       (demangling_styles): Add dlang_rust.
+       (RUST_DEMANGLING_STYLE_STRING): New macro.
+       (RUST_DEMANGLING): New macro.
+       (rust_demangle): New prototype.
+       (rust_is_mangled): Likewise.
+       (rust_demangle_sym): Likewise.
+
+2016-11-07  Jason Merrill  <jason@redhat.com>
+
+       * demangle.h (enum demangle_component_type): Add
+       DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
+
+2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
+       AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
+       (enum aarch64_op): Add OP_FCMLA_ELEM.
+
+2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
+       (enum aarch64_insn_class): Add ldst_imm10.
+
+2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
+
+2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
+       (AARCH64_ARCH_V8_3): Define.
+       (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
+
+2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
+       (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
+       (ARM_ARCH_V8M_MAIN_DSP): Likewise.
+
+2016-11-03  Graham Markall  <graham.markall@embecosm.com>
+
+       * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
+
 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 
        * opcode/arc.h (struct arc_opcode): Change type of opcode and mask