+2018-12-11 Nick Clifton <nickc@redhat.com>
+
+ PR 88409
+ * demangle.h (DEMANGLE_RECURSION_LIMIT): Increase to 2048.
+
+2018-12-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * bfdlink.h (bfd_link_info): Add has_map_file.
+
+2018-12-07 Nick Clifton <nickc@redhat.com>
+
+ * demangle.h (DMGL_NO_RECURSE_LIMIT): Define.
+ (DEMANGLE_RECURSION_LIMIT): Define
+
+2018-12-06 Alan Modra <amodra@gmail.com>
+
+ * opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
+
+2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * dis-asm.h (riscv_symbol_is_valid): Declare.
+ * opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
+ (RISCV_FAKE_LABEL_CHAR): Define.
+
+2018-12-03 Kito Cheng <kito@andestech.com>
+
+ * opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
+ unsigned.
+
+2018-11-27 Jim Wilson <jimw@sifive.com>
+
+ * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New.
+ (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New.
+
+2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M.
+ (ARM_ARCH_V6M_ONLY): Remove.
+ (ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M,
+ ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP,
+ ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8,
+ ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM,
+ ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M,
+ ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP,
+ ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN,
+ ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M,
+ ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A,
+ ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A,
+ ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK,
+ ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG,
+ FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD,
+ FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3,
+ FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
+ FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8,
+ FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD,
+ FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2,
+ ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4,
+ ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5,
+ ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE,
+ ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ,
+ ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2,
+ ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R,
+ ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM,
+ ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A,
+ ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A,
+ ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN,
+ ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE,
+ ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R,
+ ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16,
+ FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16,
+ FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8,
+ FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA,
+ FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2,
+ FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16,
+ FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1,
+ FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4,
+ FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16,
+ FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8,
+ FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8,
+ FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
+ FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2,
+ ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4,
+ ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5,
+ ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE,
+ ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ,
+ ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2,
+ ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE,
+ ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A,
+ ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A,
+ ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN,
+ ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
+ (aarch64_insn_class): Add ldstgv_indexed.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
+ and AARCH64_OPND_ADDR_SIMM13.
+ (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (aarch64_opnd): Add
+ AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
+
+2018-11-07 Roman Bolshakov <r.bolshakov@yadro.com>
+ Saagar Jha <saagar@saagarjha.com>
+
+ * mach-o/external.h (mach_o_nversion_min_command_external): Rename
+ reserved to sdk.
+ (mach_o_note_command_external): New.
+ (mach_o_build_version_command_external): New.
+ * mach-o/loader.h (BFD_MACH_O_LC_VERSION_MIN_TVOS): Define.
+ (BFD_MACH_O_LC_NOTE): Define.
+
+2018-11-06 Romain Margheriti <lilrom13@gmail.com>
+
+ PR 23742
+ * mach-o/loader.h: Add BFD_MACH_O_LC_BUILD_VERSION.
+
+2018-11-06 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
+ ARM_EXT2_SB to ...
+ (ARM_AEXT2_V8_5A): Here.
+
+2018-10-26 John Baldwin <jhb@FreeBSD.org>
+
+ * elf/common.h (AT_FREEBSD_HWCAP2): Define.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
+ (AARCH64_FEATURE_ID_PFR2): New.
+ (AARCH64_ARCH_V8_5): Add both by default.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
+ (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
+ (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
+ define HINT #imm values.
+ (HINT_OPD_JC, HINT_OPD_NULL): Likewise.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
+ (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
+ (aarch64_sys_regs_sr): Declare new table.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SB): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
+ (AARCH64_FEATURE_FRINTTS): New.
+ (AARCH64_ARCH_V8_5): Add both by default.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
+ (AARCH64_ARCH_V8_5): New.
+
+2018-10-08 Alan Modra <amodra@gmail.com>
+
+ * bfdlink.h (struct bfd_link_info): Add load_phdrs field.
+
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/arm.h (ARM_EXT2_PREDRES): New.
+ (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
+
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/arm.h (ARM_EXT2_SB): New.
+ (ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
+
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/arm.h (ARM_EXT2_V8_5A): New.
+ (ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
+
+2018-10-05 Richard Henderson <rth@twiddle.net>
+
+ * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
+ R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
+ R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
+ R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
+ R_OR1K_SLO13, R_OR1K_PLTA26.
+
+2018-10-05 Richard Henderson <rth@twiddle.net>
+
+ * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
+ R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
+ R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (aarch64_inst): Remove.
+ (enum err_type): Add ERR_VFI.
+ (aarch64_is_destructive_by_operands): New.
+ (init_insn_sequence): New.
+ (aarch64_decode_insn): Remove param name.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
+ more arguments.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (enum err_type): New.
+ (aarch64_decode_insn): Use it.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (struct aarch64_instr_sequence): New.
+ (aarch64_opcode_encode): Use it.
+
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h (struct aarch64_opcode): Add constraints,
+ extend flags field size.
+ (F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
+
+2018-10-03 John Darrington <john@darrington.wattle.id.au>
+
+ * dis-asm.h (print_insn_s12z): New declaration.
+
+2018-10-02 Palmer Dabbelt <palmer@sifive.com>
+
+ * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
+ (MASK_FENCE_TSO): Likewise.
+
+2018-10-01 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.
+
+2018-09-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/23694
+ * include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
+ include zero size sections at start of PT_NOTE segment.
+
+2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
+
+ * elf/nds32.h: Remove the unused target features.
+ * dis-asm.h (disassemble_init_nds32): Declared.
+ * elf/nds32.h (E_NDS32_NULL): Removed.
+ (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
+ * opcode/nds32.h: Ident.
+ (N32_SUB6, INSN_LW): New macros.
+ (enum n32_opcodes): Updated.
+ * elf/nds32.h: Doc fixes.
+ * elf/nds32.h: Add R_NDS32_LSI.
+ * elf/nds32.h: Add new relocations for TLS.
+
+2018-09-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ * elf/common.h (AT_SUN_HWCAP): Rename to ...
+ (AT_SUN_CAP_HW1): ... this. Retain old name for backward
+ compatibility.
+ (AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1)
+ (AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.
+
+2018-09-05 Simon Marchi <simon.marchi@ericsson.com>
+
+ * diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
+
+2018-08-31 Alan Modra <amodra@gmail.com>
+
+ * elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
+ (R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
+ (R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
+ (R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
+
+2018-08-30 Kito Cheng <kito@andestech.com>
+
+ * opcode/riscv.h (MAX_SUBSET_NUM): New.
+ (riscv_opcode): Add xlen_requirement field and change type of
+ subset.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
+ * opcode/mips.h (CPU_XXX): New CPU_GS264E.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
+ * opcode/mips.h (CPU_XXX): New CPU_GS464E.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
+ E_MIPS_MACH_GS464.
+ (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
+ * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
+ (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
+ * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
+ * opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
+ * opcode/mips.h (ASE_LOONGSON_EXT): New macro.
+
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
projects / deliverable / binutils-gdb.git / blobdiff