-2019-05-28 Nick Alcock <nick.alcock@oracle.com>
+2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
- * ctf-api.h: New file.
+ * elf/xtensa.h (xtensa_abi_choice): New declaration.
-2019-05-28 Nick Alcock <nick.alcock@oracle.com>
+2020-06-12 Roland McGrath <mcgrathr@google.com>
- * ctf.h: New file.
+ * bfdlink.h (struct bfd_link_info): New field start_stop_visibility.
-2019-05-24 Szabolcs Nagy <szabolcs.nagy@arm.com>
+2020-06-12 Nelson Chu <nelson.chu@sifive.com>
- * elf/aarch64.h (DT_AARCH64_VARIANT_PCS): Define.
- (STO_AARCH64_VARIANT_PCS): Define.
+ * opcode/riscv-opc.h: Update the defined versions of CSR from
+ PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the
+ MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9.
+ * opcode/riscv.h (enum riscv_priv_spec_class): Remove
+ PRIV_SPEC_CLASS_1P9.
-2019-05-24 Alan Modra <amodra@gmail.com>
+2020-06-11 Alex Coplan <alex.coplan@arm.com>
- * elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
- (R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
- (R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
- (R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
- (R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
- (R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
- (R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
- (R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
- (R_PPC64_D28, R_PPC64_PCREL28): Define.
+ * opcode/aarch64.h (aarch64_sys_reg): Add required features to struct
+ describing system registers.
-2019-05-24 Peter Bergner <bergner@linux.ibm.com>
- Alan Modra <amodra@gmail.com>
+2020-06-11 Alan Modra <amodra@gmail.com>
- * dis-asm.h (WIDE_OUTPUT): Define.
- * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
- (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
- (PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
+ * elf/mips.h (Elf32_RegInfo): Use fixed width integer types.
+ (Elf64_Internal_RegInfo, Elf_Internal_Options): Likewise.
-2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
+2020-06-06 Alan Modra <amodra@gmail.com>
- * elf/bpf.h: New file.
+ * elf/ppc64.h (elf_ppc64_reloc_type): Rename
+ R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
+ R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
+ R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
+ R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
-2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
- * elf/arm.h (Tag_MVE_arch): Define new enum value.
- * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
+ * opcode/cgen.h: Get an `endian' argument in both
+ cgen_get_insn_value and cgen_put_insn_value.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
- operand.
+ * opcode/cgen.h (enum cgen_cpu_open_arg): New value
+ CGEN_CPU_OPEN_INSN_ENDIAN.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-06-03 Nelson Chu <nelson.chu@sifive.com>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
- iclass.
+ * opcode/riscv.h: Remove #include "bfd.h". And change the return
+ types of riscv_get_isa_spec_class and riscv_get_priv_spec_class
+ from bfd_boolean to int.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-05-28 Alan Modra <amodra@gmail.com>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
+ PR 26044
+ * opcode/tilepro.h (TILEPRO_NUM_PIPELINE_ENCODINGS): Move to
+ tilepro_pipeline enum.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-05-27 H.J. Lu <hongjiu.lu@intel.com>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
- iclass.
+ PR ld/22909
+ * bfdlink.h (textrel_check_method): New enum.
+ (bfd_link_textrel_check): New.
+ (bfd_link_info): Replace warn_shared_textrel and error_textrel
+ with textrel_check.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
- operand.
- (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
+ * elf/common.h: Update comments for ET_EXEC and ET_DYN.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-05-20 Nelson Chu <nelson.chu@sifive.com>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
+ * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
+ (enum riscv_isa_spec_class): New enum class. All supported ISA spec
+ belong to one of the class
+ (struct riscv_ext_version): New structure holds version information
+ for the specific ISA.
+ * opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
+ define_version and abort_version. The define_version means which
+ privilege spec is started to define the CSR, and the abort_version
+ means which privilege spec is started to abort the CSR. If the CSR is
+ valid for the newest spec, then the abort_version should be
+ PRIV_SPEC_CLASS_DRAFT.
+ (DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
+ * opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
+ the current supported privilege spec versions.
+ (struct riscv_csr_extra): Add new fields to store more information
+ about the CSR. We use these information to find the suitable CSR
+ address when user choosing a specific privilege spec.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-05-19 Alexander Fedotov <alfedotov@gmail.com>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
+ PR 25992
+ * opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-05-11 Alan Modra <amodra@gmail.com>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.
+ * opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following
+ PPC_OPERAND defines.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-05-11 Alan Modra <amodra@gmail.com>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
+ * elf/ppc64.h: Update comment.
+ * opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-04-30 Alex Coplan <alex.coplan@arm.com>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
+ * opcode/aarch64.h (enum aarch64_opnd): Add
+ AARCH64_OPND_UNDEFINED.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-04-23 Anton Kolesov <anton.kolesov@synopsys.com>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
+ * elf/common.h (NT_ARC_V2): New macro definitions.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
+ PR ld/25861
+ * elf/xtensa.h (elf_xtensa_reloc_type): New entries for
+ R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-04-21 Alan Modra <amodra@gmail.com>
- * opcode/aarch64.h (AARCH64_FEATURE_SVE2
- AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
- AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
- feature macros.
+ * elf/sh.h (STO_SH5_ISA32, SHF_SH5_ISA32, SHF_SH5_ISA32_MIXED),
+ (SHT_SH5_CR_SORTED, STT_DATALABEL): Delete.
-2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
- Faraz Shahbazker <fshahbazker@wavecomp.com>
+2020-04-10 Fangrui Song <maskray@google.com>
- * opcode/mips.h (ASE_EVA_R6): New macro.
- (M_LLWPE_AB, M_SCWPE_AB): New enum values.
+ PR binutils/24613
+ * bfdlink.h (enum report_method): Delete RM_GENERATE_WARNING and
+ RM_GENERATE_ERROR. Add RM_DIAGNOSE.
+ (struct bfd_link_info): Add warn_unresolved_syms.
-2019-05-01 Sudakshina Das <sudi.das@arm.com>
+2020-04-14 Stephen Casner <casner@acm.org>
- * opcode/aarch64.h (AARCH64_FEATURE_TME): New.
- (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
+ PR ld/25677
+ * aout/aout64.h (N_DATADDR): Add IMAGIC case.
-2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
- Faraz Shahbazker <fshahbazker@wavecomp.com>
+2020-04-02 Jan W. Jagersma <jwjagersma@gmail.com>
- * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
- (M_SCWP_AB, M_SCDP_AB): Likewise.
+ * coff/go32exe.h: Remove file.
+ * coff/internal.h (struct internal_filehdr): Remove field
+ go32stub. Remove flag F_GO32STUB.
-2019-04-25 Maciej W. Rozycki <macro@linux-mips.org>
+2020-04-01 Martin Liska <mliska@suse.cz>
+ Maciej W. Rozycki <macro@linux-mips.org>
- * opcode/mips.h: Update comment for MIPS32 CODE20 operand.
+ PR lto/94249
+ * plugin-api.h: Fix a typo.
-2019-04-15 Sudakshina Das <sudi.das@arm.com>
+2020-03-30 Nelson Chu <nelson.chu@sifive.com>
- * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
+ * opcode/riscv-opc.h: Update CSR to 1.11.
-2019-04-15 Sudakshina Das <sudi.das@arm.com>
+2020-03-26 John Baldwin <jhb@FreeBSD.org>
- * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
+ * elf/common.h (AT_FREEBSD_BSDFLAGS): Define.
-2019-04-15 Sudakshina Das <sudi.das@arm.com>
+2020-03-24 Martin Liska <mliska@suse.cz>
- * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
+ PR lto/94249
+ * plugin-api.h: Add more robust endianess detection.
-2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+2020-03-21 Martin Liska <mliska@suse.cz>
- * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
- (MAX_TAG_CPU_ARCH): Set value to above macro.
- * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
- (ARM_AEXT_V8_1M_MAIN): Likewise.
- (ARM_AEXT2_V8_1M_MAIN): Likewise.
- (ARM_ARCH_V8_1M_MAIN): Likewise.
+ * plugin-api.h (enum ld_plugin_symbol_type): Remove
+ comma after last value of an enum.
+ * lto-symtab.h (enum gcc_plugin_symbol_type): Likewise.
-2019-04-11 Sudakshina Das <sudi.das@arm.com>
+2020-03-19 Martin Liska <mliska@suse.cz>
- * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
+ * lto-symtab.h (enum gcc_plugin_symbol_type): New.
+ (enum gcc_plugin_symbol_section_kind): Likewise.
-2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
+2020-03-19 Martin Liska <mliska@suse.cz>
- * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
+ * plugin-api.h (struct ld_plugin_symbol): Split
+ int def into 4 char fields.
+ (enum ld_plugin_symbol_type): New.
+ (enum ld_plugin_symbol_section_kind): New.
+ (enum ld_plugin_tag): Add LDPT_ADD_SYMBOLS_V2.
-2019-04-07 Alan Modra <amodra@gmail.com>
+2020-03-13 Kamil Rytarowski <n54@gmx.com>
- Merge from gcc.
- 2019-04-03 Vineet Gupta <vgupta@synopsys.com>
- PR89877
- * longlong.h [__arc__] (add_ssaaaa): Add cc clobber.
- (sub_ddmmss): Likewise.
+ * elf/common.h (NT_NETBSDCORE_LWPSTATUS): New define.
-2019-04-06 H.J. Lu <hongjiu.lu@intel.com>
+2020-03-13 Kamil Rytarowski <n54@gmx.com>
- * bfdlink.h (bfd_link_info): Remove x86-specific linker options.
+ * elf/common.h (NT_NETBSDCORE_AUXV): New define.
-2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
+2020-03-13 Christophe Lyon <christophe.lyon@linaro.org>
- * opcode/arm.h (FPU_NEON_ARMV8_1): New.
- (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.
- (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.
- (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.
- (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.
- (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.
- (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.
- (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.
+ * bfdlink.h (bfd_link_info): Add non_contiguous_regions and
+ non_contiguous_regions_warnings fields.
-2019-03-28 Alan Modra <amodra@gmail.com>
+2020-03-13 Christian Eggers <ceggers@gmx.de>
- PR 24390
- * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
+ * bfdlink.h (struct bfd_link_order): Add unit (bytes/octets) to
+ offset and size members.
+ * elf/internal.h (struct elf_internal_phdr): Likewise for
+ p_align member.
+ (struct elf_segment_map): Likewise for p_paddr and p_size
+ members
-2019-03-25 Tamar Christina <tamar.christina@arm.com>
+2020-03-13 Christian Eggers <ceggers@gmx.de>
- * dis-asm.h (struct disassemble_info): Add stop_offset.
+ * elf/internal.h (struct elf_internal_phdr): Add unit (octets)
+ to several member field comments.
+ (Elf_Internal_Shdr): likewise.
-2019-03-13 Sudakshina Das <sudi.das@arm.com>
+2020-03-10 Alan Modra <amodra@gmail.com>
- * elf/aarch64.h (DT_AARCH64_PAC_PLT): New.
+ * som/aout.h (SOM_AUX_ID_MANDATORY, SOM_SPACE_IS_LOADABLE),
+ (SOM_SYMBOL_HIDDEN, SOM_SYMBOL_HAS_LONG_RETURN): Use 1u << 31.
+ * som/lst.h (LST_SYMBOL_HIDDEN): Likewise.
-2019-03-13 Sudakshina Das <sudi.das@arm.com>
- Szabolcs Nagy <szabolcs.nagy@arm.com>
+2020-03-03 Luis Machado <luis.machado@linaro.org>
- * elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
+ * elf/common.h (AT_L1I_CACHESIZE, AT_L1I_CACHEGEOMETRY)
+ (AT_L1D_CACHESIZE, AT_L1D_CACHEGEOMETRY, AT_L2_CACHESIZE)
+ (AT_L2_CACHEGEOMETRY, AT_L3_CACHESIZE, AT_L3_CACHEGEOMETRY)
+ (AT_MINSIGSTKSZ): New defines, imported from glibc.
-2019-03-13 Sudakshina Das <sudi.das@arm.com>
+2020-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
- * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
- (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
- (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.
+ Import from gcc mainline:
+ 2020-02-05 Andrew Burgess <andrew.burgess@embecosm.com>
-2019-02-20 Alan Hayward <alan.hayward@arm.com>
+ * hashtab.h (htab_remove_elt): Make a parameter const.
+ (htab_remove_elt_with_hash): Likewise.
- * elf/common.h (NT_ARM_PAC_MASK): Add define.
+2020-02-20 Nelson Chu <nelson.chu@sifive.com>
-2019-02-15 Saagar Jha <saagar@saagarjha.com>
+ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
+ record riscv_csr_class.
- * mach-o/loader.h: Use new OS names in comments.
+2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
+ Matthew Malcomson <matthew.malcomson@arm.com>
-2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be>
+ * opcode/arm.h (ARM_EXT2_CDE): New extension macro.
+ (ARM_EXT2_CDE0): New extension macro.
+ (ARM_EXT2_CDE1): New extension macro.
+ (ARM_EXT2_CDE2): New extension macro.
+ (ARM_EXT2_CDE3): New extension macro.
+ (ARM_EXT2_CDE4): New extension macro.
+ (ARM_EXT2_CDE5): New extension macro.
+ (ARM_EXT2_CDE6): New extension macro.
+ (ARM_EXT2_CDE7): New extension macro.
- * splay-tree.h (splay_tree_delete_key_fn): Update comment.
- (splay_tree_delete_value_fn): Likewise.
+2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
-2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
+ PR 25469
+ * coff/internal.h (R_IMM16BE): Define.
+ * elf/z80.h (EF_Z80_MACH_Z80N): Define.
+ (R_Z80_16_BE): New reloc.
- * opcode/s390.h (enum s390_opcode_cpu_val): Add
- S390_OPCODE_ARCH13.
+2020-02-04 Alan Modra <amodra@gmail.com>
-2019-01-25 Sudakshina Das <sudi.das@arm.com>
- Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ * opcode/d30v.h (struct pd_reg): Make value field unsigned.
- * opcode/aarch64.h (enum aarch64_opnd): Remove
- AARCH64_OPND_ADDR_SIMPLE_2.
- (enum aarch64_insn_class): Remove ldstgv_indexed.
+2020-01-16 Jon Turney <jon.turney@dronecode.org.uk>
-2019-01-22 Tom Tromey <tom@tromey.com>
+ * coff/internal.h (PE_IMAGE_DEBUG_TYPE_VC_FEATURE)
+ (PE_IMAGE_DEBUG_TYPE_POGO, PE_IMAGE_DEBUG_TYPE_ILTCG)
+ (PE_IMAGE_DEBUG_TYPE_MPX, PE_IMAGE_DEBUG_TYPE_REPRO): Add.
- * coff/ecoff.h: Include coff/sym.h.
+2020-01-18 Nick Clifton <nickc@redhat.com>
-2018-06-24 Nick Clifton <nickc@redhat.com>
+ Binutils 2.34 branch created.
- 2.32 branch created.
+2020-01-17 Nick Clifton <nickc@redhat.com>
-2019-01-16 Kito Cheng <kito@andestech.com>
+ * Import from gcc mainline:
+ 2019-06-10 Martin Liska <mliska@suse.cz>
- * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
- (Tag_RISCV_arch): Likewise.
- (Tag_RISCV_priv_spec): Likewise.
- (Tag_RISCV_priv_spec_minor): Likewise.
- (Tag_RISCV_priv_spec_revision): Likewise.
- (Tag_RISCV_unaligned_access): Likewise.
- (Tag_RISCV_stack_align): Likewise.
+ * ansidecl.h (ATTRIBUTE_WARN_UNUSED_RESULT): New macro.
+ * libiberty.h (xmalloc): Use it.
+ (xrealloc): Likewise.
+ (xcalloc): Likewise.
+ (xstrdup): Likewise.
+ (xstrndup): Likewise.
+ (xmemdup): Likewise.
-2019-01-14 Pavel I. Kryukov <kryukov@frtk.ru>
+ 2019-06-10 Martin Liska <mliska@suse.cz>
- * dis-asm.h: include <string.h>
+ * ansidecl.h:
+ (ATTRIBUTE_RESULT_SIZE_1): Define new macro.
+ (ATTRIBUTE_RESULT_SIZE_2): Likewise.
+ (ATTRIBUTE_RESULT_SIZE_1_2): Likewise.
+ * libiberty.h (xmalloc): Add RESULT_SIZE attribute.
+ (xrealloc): Likewise.
+ (xcalloc): Likewise.
-2019-01-10 Nick Clifton <nickc@redhat.com>
+ 2019-11-16 Tim Ruehsen <tim.ruehsen@gmx.de>
- * Merge from GCC:
- 2018-12-22 Jason Merrill <jason@redhat.com>
+ * demangle.h (struct demangle_component): Add member
+ d_counting.
- * demangle.h: Remove support for ancient GNU (pre-3.0), Lucid,
- ARM, HP, and EDG demangling styles.
+ 2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs>
-2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
+ * demangle.h (rust_demangle_callback): Add.
- Merge from GCC:
- PR other/16615
+ 2019-07-18 Eduard-Mihai Burtescu <eddyb@lyken.rs>
- * libiberty.h: Mechanically replace "can not" with "cannot".
- * plugin-api.h: Likewise.
+ * demangle.h (rust_is_mangled): Move to libiberty/rust-demangle.h.
+ (rust_demangle_sym): Move to libiberty/rust-demangle.h.
-2018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp>
+2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
- * elf/rx.h (EF_RX_CPU_MASK): Update new bits.
- (E_FLAG_RX_V3): New RXv3 type.
- * opcode/rx.h (RX_Size): Add double size.
- (RX_Operand_Type): Add double FPU registers.
- (RX_Opcode_ID): Add new instuctions.
+ PR 25376
+ * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
+ (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
+ (ARM_ANY): Redefine to not include any MVE bits.
+ (ARM_FEATURE_ALL): Removed.
-2019-01-01 Alan Modra <amodra@gmail.com>
+2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * opcode/msp430.h (enum msp430_expp_e): New.
+ (struct msp430_operand_s): Add expp member to struct.
+
+2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
+
+ * elf/arc-cpu.def: Update ARC cpu list.
+
+2020-01-13 Alan Modra <amodra@gmail.com>
+
+ * opcode/tic4x.h (EXTR): Delete.
+ (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
+ extension using shifts. Do trim INSERTU value to specified bitfield.
+
+2020-01-10 Alan Modra <amodra@gmail.com>
+
+ * opcode/spu.h: Formatting.
+ (UNSIGNED_EXTRACT): Use 1u.
+ (SIGNED_EXTRACT): Don't sign extend with shifts.
+ (DECODE_INSN_I9a, DECODE_INSN_I9b): Avoid left shift of signed value.
+ Keep result signed.
+ (DECODE_INSN_U9a, DECODE_INSN_U9b): Delete.
+
+2020-01-07 Shahab Vahedi <shahab@synopsys.com>
+
+ * opcode/arc.h (insn_class_t): Add 'LLOCK' and 'SCOND'.
+
+2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ * coff/internal.h: Add defintions of Z80 reloc names.
+
+2020-01-02 Christian Biesinger <cbiesinger@google.com>
+
+ * opcode/s12z.h: Undef REG_Y.
+
+2020-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
-For older changes see ChangeLog-2018
+For older changes see ChangeLog-2019
\f
-Copyright (C) 2019 Free Software Foundation, Inc.
+Copyright (C) 2020 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff