-2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
- * dis-asm.h (struct disassemble_info): Change type of buffer_length
- field to size_t.
+ * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
-2017-07-07 John Baldwin <jhb@FreeBSD.org>
+2018-11-07 Roman Bolshakov <r.bolshakov@yadro.com>
+ Saagar Jha <saagar@saagarjha.com>
- * elf/common.h (NT_FREEBSD_PTLWPINFO): Define.
+ * mach-o/external.h (mach_o_nversion_min_command_external): Rename
+ reserved to sdk.
+ (mach_o_note_command_external): New.
+ (mach_o_build_version_command_external): New.
+ * mach-o/loader.h (BFD_MACH_O_LC_VERSION_MIN_TVOS): Define.
+ (BFD_MACH_O_LC_NOTE): Define.
-2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com>
+2018-11-06 Romain Margheriti <lilrom13@gmail.com>
- * dwarf2.def (DW_IDX_compile_unit, DW_IDX_type_unit, DW_IDX_die_offset)
- (DW_IDX_parent, DW_IDX_type_hash, DW_IDX_lo_user, DW_IDX_hi_user)
- (DW_IDX_GNU_internal, DW_IDX_GNU_external): New.
- * dwarf2.h (DW_IDX, DW_IDX_DUP, DW_FIRST_IDX, DW_END_IDX): New.
- (enum dwarf_name_index_attribute): Remove.
- (get_DW_IDX_name): New declaration.
+ PR 23742
+ * mach-o/loader.h: Add BFD_MACH_O_LC_BUILD_VERSION.
-2017-06-30 Georg-Johann Lay <avr@gjlay.de>
+2018-11-06 Sudakshina Das <sudi.das@arm.com>
- PR gas/21683
- * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
+ * opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
+ ARM_EXT2_SB to ...
+ (ARM_AEXT2_V8_5A): Here.
-2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
- Andrew Bennett <andrew.bennett@imgtec.com>
+2018-10-26 John Baldwin <jhb@FreeBSD.org>
- * opcode/mips.h (ASE_XPA_VIRT): New macro.
+ * elf/common.h (AT_FREEBSD_HWCAP2): Define.
-2017-06-29 Andreas Arnez <arnez@linux.vnet.ibm.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * elf/common.h (NT_S390_GS_CB): New macro.
- (NT_S390_GS_BC): Likewise.
+ * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
-2017-06-28 Tamar Christina <tamar.christina@arm.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New.
- (aarch64_insn_class): Added dotprod.
+ * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
+ (AARCH64_FEATURE_ID_PFR2): New.
+ (AARCH64_ARCH_V8_5): Add both by default.
-2017-06-28 Jiong Wang <jiong.wang@arm.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
- (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.
+ * opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
+ (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
+ (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
+ define HINT #imm values.
+ (HINT_OPD_JC, HINT_OPD_NULL): Likewise.
-2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
- Matthew Fortune <matthew.fortune@imgtec.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
- (AFL_EXT_INTERAPTIV_MR2): Likewise.
- * opcode/mips.h: Document new operand codes defined.
- (INSN_INTERAPTIV_MR2): New macro.
- (INSN_CHIP_MASK): Adjust accordingly.
- (CPU_INTERAPTIV_MR2): New macro.
- (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
- (MIPS16_ALL_ARGS): Rename to...
- (MIPS_SVRS_ALL_ARGS): ... this.
- (MIPS16_ALL_STATICS): Rename to...
- (MIPS_SVRS_ALL_STATICS): ... this.
+ * opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
-2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * elf/riscv.h (R_RISCV_32_PCREL): New.
+ * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
-2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
- * opcode/arm.h (ARM_EXT2_V8A): New macro.
- (ARM_AEXT2_V8A): Rename into ...
- (ARM_AEXT2_V8AR): This.
- (ARM_AEXT2_V8A): New macro.
- (ARM_AEXT_V8R): New macro.
- (ARM_AEXT2_V8R): New macro.
- (ARM_ARCH_V8R): New macro.
+ * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
+ (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
+ (aarch64_sys_regs_sr): Declare new table.
-2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
- (ARM_AEXT_V4T): Likewise.
- (ARM_AEXT_V5TxM): Likewise.
- (ARM_AEXT_V5T): Likewise.
- (ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
+ * opcode/aarch64.h (AARCH64_FEATURE_SB): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
-2017-06-22 H.J. Lu <hongjiu.lu@intel.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * bfdlink.h (bfd_link_info): Add shstk.
- * elf/common.h (GNU_PROPERTY_X86_FEATURE_1_SHSTK): New.
+ * opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
+ (AARCH64_FEATURE_FRINTTS): New.
+ (AARCH64_ARCH_V8_5): Add both by default.
-2017-06-22 H.J. Lu <hongjiu.lu@intel.com>
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
- * bfdlink.h (bfd_link_info): Add ibtplt and ibt.
- * elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New.
- (GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise.
+ * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
+ (AARCH64_ARCH_V8_5): New.
-2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
+2018-10-08 Alan Modra <amodra@gmail.com>
- * opcode/arm.h (FPU_ANY): New macro.
+ * bfdlink.h (struct bfd_link_info): Add load_phdrs field.
-2017-06-20 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
- * elf/s390.h (PT_S390_PGSTE): Define macro.
+ * opcode/arm.h (ARM_EXT2_PREDRES): New.
+ (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
-2017-06-16 Alan Modra <amodra@gmail.com>
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
- PR ld/20022
- PR ld/21557
- PR ld/21562
- PR ld/21571
- * bfdlink.h (struct bfd_link_hash_entry): Delete undef.section.
+ * opcode/arm.h (ARM_EXT2_SB): New.
+ (ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
-2017-06-14 Yao Qi <yao.qi@linaro.org>
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
- * dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
- (print_insn_big_arm, print_insn_big_mips): Likewise.
- (print_insn_i386, print_insn_ia64): Likewise.
- (print_insn_little_arm, print_insn_little_mips): Likewise.
- (print_insn_spu): Likewise.
+ * opcode/arm.h (ARM_EXT2_V8_5A): New.
+ (ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
-2017-06-06 Andrew Burgess <andrew.burgess@embecosm.com>
+2018-10-05 Richard Henderson <rth@twiddle.net>
- * bfdlink.h (struct bfd_link_info): Add new resolve_section_groups
- flag.
+ * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
+ R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
+ R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
+ R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
+ R_OR1K_SLO13, R_OR1K_PLTA26.
-2017-06-01 Alan Modra <amodra@gmail.com>
+2018-10-05 Richard Henderson <rth@twiddle.net>
- * elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define.
+ * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
+ R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
+ R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
-2017-05-31 Eli Zaretskii <eliz@gnu.org>
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
- * environ.h: Add #ifndef guard.
+ * opcode/aarch64.h (aarch64_inst): Remove.
+ (enum err_type): Add ERR_VFI.
+ (aarch64_is_destructive_by_operands): New.
+ (init_insn_sequence): New.
+ (aarch64_decode_insn): Remove param name.
-2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
- * elf/arc-cpu.def: New file.
+ * opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
+ more arguments.
-2017-05-24 Yao Qi <yao.qi@linaro.org>
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
- * dis-asm.h: Move some function declarations to
- opcodes/disassemble.h.
+ * opcode/aarch64.h (enum err_type): New.
+ (aarch64_decode_insn): Use it.
-2017-05-24 Yao Qi <yao.qi@linaro.org>
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
- * dis-asm.h (disassembler): Update declaration.
+ * opcode/aarch64.h (struct aarch64_instr_sequence): New.
+ (aarch64_opcode_encode): Use it.
-2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
+2018-10-03 Tamar Christina <tamar.christina@arm.com>
- * opcode/arc.h (MAX_INSN_FLGS): Update to 4.
+ * opcode/aarch64.h (struct aarch64_opcode): Add constraints,
+ extend flags field size.
+ (F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
-2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
+2018-10-03 John Darrington <john@darrington.wattle.id.au>
- * include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.
+ * dis-asm.h (print_insn_s12z): New declaration.
-2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
+2018-10-02 Palmer Dabbelt <palmer@sifive.com>
- * elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
- (ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
- (ELF_SPARC_HWCAP2_ONMUL): Likewise.
- (ELF_SPARC_HWCAP2_ONDIV): Likewise.
- (ELF_SPARC_HWCAP2_DICTUNP): Likewise.
- (ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
- (ELF_SPARC_HWCAP2_RLE): Likewise.
- (ELF_SPARC_HWCAP2_SHA3): Likewise.
- * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
- and adjust SPARC_OPCODE_ARCH_MAX.
- (HWCAP2_SPARC6): Define.
- (HWCAP2_ONADDSUB): Likewise.
- (HWCAP2_ONMUL): Likewise.
- (HWCAP2_ONDIV): Likewise.
- (HWCAP2_DICTUNP): Likewise.
- (HWCAP2_FPCMPSHL): Likewise.
- (HWCAP2_RLE): Likewise.
- (HWCAP2_SHA3): Likewise.
- (OPM): Likewise.
- (OPMI): Likewise.
- (ONFCN): Likewise.
- (REVFCN): Likewise.
- (SIMM10): Likewise.
+ * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
+ (MASK_FENCE_TSO): Likewise.
-2017-05-16 Alan Modra <amodra@gmail.com>
+2018-10-01 Cupertino Miranda <cmiranda@synopsys.com>
- * bfdlink.h (struct bfd_link_hash_entry <non_ir_ref>): Rename to
- non_ir_ref_regular.
+ * arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.
-2017-05-16 Alan Modra <amodra@gmail.com>
+2018-09-21 H.J. Lu <hongjiu.lu@intel.com>
- * bfdlink.h (struct bfd_link_hash_entry): Update non_ir_ref
- comment. Rename dynamic_ref_after_ir_def to non_ir_ref_dynamic.
+ PR binutils/23694
+ * include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
+ include zero size sections at start of PT_NOTE segment.
-2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
- Matthew Fortune <matthew.fortune@imgtec.com>
+2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
- * elf/mips.h (AFL_ASE_MIPS16E2): New macro.
- (AFL_ASE_MASK): Adjust accordingly.
- * opcode/mips.h: Document new operand codes defined.
- (mips_operand_type): Add OP_REG28 enum value.
- (INSN2_SHORT_ONLY): Update description.
- (ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
+ * elf/nds32.h: Remove the unused target features.
+ * dis-asm.h (disassemble_init_nds32): Declared.
+ * elf/nds32.h (E_NDS32_NULL): Removed.
+ (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
+ * opcode/nds32.h: Ident.
+ (N32_SUB6, INSN_LW): New macros.
+ (enum n32_opcodes): Updated.
+ * elf/nds32.h: Doc fixes.
+ * elf/nds32.h: Add R_NDS32_LSI.
+ * elf/nds32.h: Add new relocations for TLS.
-2017-05-14 John David Anglin <danglin@gcc.gnu.org>
+2018-09-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
- * opcode/hppa.h: Fix match and mask for 64-bit bb opcode.
+ * elf/common.h (AT_SUN_HWCAP): Rename to ...
+ (AT_SUN_CAP_HW1): ... this. Retain old name for backward
+ compatibility.
+ (AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1)
+ (AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.
-2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
-
- * elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
- (Tag_ARC_*): Define.
- (E_ARC_OSABI_V4): Define.
- (E_ARC_OSABI_CURRENT): Reassign it.
- (TAG_CPU_*): Define.
- * opcode/arc-attrs.h: New file.
- * opcode/arc.h (insn_subclass_t): Assign enum values.
- (insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
- (ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
- (ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
- (ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
- (ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
- (ARC_CRC): Delete.
+2018-09-05 Simon Marchi <simon.marchi@ericsson.com>
-2017-04-20 H.J. Lu <hongjiu.lu@intel.com>
+ * diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
- PR ld/21382
- * bfdlink.h (bfd_link_hash_entry): Add dynamic_ref_after_ir_def.
+2018-08-31 Alan Modra <amodra@gmail.com>
-2017-04-19 Alan Modra <amodra@gmail.com>
+ * elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
+ (R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
+ (R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
+ (R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
+
+2018-08-30 Kito Cheng <kito@andestech.com>
+
+ * opcode/riscv.h (MAX_SUBSET_NUM): New.
+ (riscv_opcode): Add xlen_requirement field and change type of
+ subset.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
+ * opcode/mips.h (CPU_XXX): New CPU_GS264E.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- * bfdlink.h (struct bfd_link_info <dynamic_undefined_weak>):
- Revise comment.
+ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
+ * opcode/mips.h (CPU_XXX): New CPU_GS464E.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
+ E_MIPS_MACH_GS464.
+ (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
+ * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
+ (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
+ * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
-2017-04-11 Alan Modra <amodra@gmail.com>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- * opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete.
- (PPC_OPCODE_VSX3): Delete.
- (PPC_OPCODE_HTM): Delete.
- (PPC_OPCODE_*): Renumber and order chronologically.
- (PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo.
+ * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
+ * opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
-2017-04-06 Pip Cet <pipcet@gmail.com>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- * dis-asm.h: Add prototypes for wasm32 disassembler.
+ * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
+ * opcode/mips.h (ASE_LOONGSON_EXT): New macro.
-2017-04-05 Pedro Alves <palves@redhat.com>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- * dis-asm.h (disassemble_info) <disassembler_options>: Now a
- "const char *".
- (next_disassembler_option): Constify.
+ * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
+ * opcode/mips.h (ASE_LOONGSON_CAM): New macro.
-2017-04-04 H.J. Lu <hongjiu.lu@intel.com>
+2018-08-24 H.J. Lu <hongjiu.lu@intel.com>
- * elf/common.h (PT_GNU_MBIND_NUM): New.
- (PT_GNU_MBIND_LO): Likewise.
- (PT_GNU_MBIND_HI): Likewise.
- (SHF_GNU_MBIND): Likewise.
-
-2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
-
- * elf/riscv.h (RISCV_GP_SYMBOL): New define.
-
-2017-03-27 Andrew Waterman <andrew@sifive.com>
-
- * opcode/riscv-opc.h (CSR_PMPCFG0): New define.
- (CSR_PMPCFG1): Likewise.
- (CSR_PMPCFG2): Likewise.
- (CSR_PMPCFG3): Likewise.
- (CSR_PMPADDR0): Likewise.
- (CSR_PMPADDR1): Likewise.
- (CSR_PMPADDR2): Likewise.
- (CSR_PMPADDR3): Likewise.
- (CSR_PMPADDR4): Likewise.
- (CSR_PMPADDR5): Likewise.
- (CSR_PMPADDR6): Likewise.
- (CSR_PMPADDR7): Likewise.
- (CSR_PMPADDR8): Likewise.
- (CSR_PMPADDR9): Likewise.
- (CSR_PMPADDR10): Likewise.
- (CSR_PMPADDR11): Likewise.
- (CSR_PMPADDR12): Likewise.
- (CSR_PMPADDR13): Likewise.
- (CSR_PMPADDR14): Likewise.
- (CSR_PMPADDR15): Likewise.
- (pmpcfg0): Declare register.
- (pmpcfg1): Likewise.
- (pmpcfg2): Likewise.
- (pmpcfg3): Likewise.
- (pmpaddr0): Likewise.
- (pmpaddr1): Likewise.
- (pmpaddr2): Likewise.
- (pmpaddr3): Likewise.
- (pmpaddr4): Likewise.
- (pmpaddr5): Likewise.
- (pmpaddr6): Likewise.
- (pmpaddr7): Likewise.
- (pmpaddr8): Likewise.
- (pmpaddr9): Likewise.
- (pmpaddr10): Likewise.
- (pmpaddr11): Likewise.
- (pmpaddr12): Likewise.
- (pmpaddr13): Likewise.
- (pmpaddr14): Likewise.
- (pmpaddr15): Likewise.
-
-2017-03-30 Pip Cet <pipcet@gmail.com>
-
- * opcode/wasm.h: New file to support wasm32 architecture.
- * elf/wasm32.h: Add R_WASM32_32 relocation.
-
-2017-03-29 Alan Modra <amodra@gmail.com>
-
- * opcode/ppc.h (PPC_OPCODE_RAW): Define.
- (PPC_OPCODE_*): Make them all unsigned long long constants.
-
-2017-03-27 Pip Cet <pipcet@gmail.com>
-
- * elf/wasm32.h: New file to support wasm32 architecture.
-
-2017-03-27 Rinat Zelig <rinat@mellanox.com>
-
- * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
-
-2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
-
- * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
- (S390_INSTR_FLAG_FACILITY_MASK): Adjust value.
-
-2017-03-21 Rinat Zelig <rinat@mellanox.com>
-
- * opcode/arc.h (insn_class_t): Add DMA class.
-
-2017-03-16 Nick Clifton <nickc@redhat.com>
-
- * elf/common.h (GNU_BUILD_ATTRIBUTE_SHORT_ENUM): New GNU BUILD
- note type.
-
-2017-03-14 Jakub Jelinek <jakub@redhat.com>
-
- PR debug/77589
- * dwarf2.def (DW_OP_GNU_variable_value): New opcode.
-
-2017-03-13 Markus Trippelsdorf <markus@trippelsdorf.de>
-
- PR demangler/70909
- PR demangler/67264
- * demangle.h (struct demangle_component): Add d_printing field.
- (cplus_demangle_print): Remove const qualifier from tree
- parameter.
- (cplus_demangle_print_callback): Likewise.
-
-2017-03-13 Nick Clifton <nickc@redhat.com>
-
- PR binutils/21202
- * elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
- R_AARCH64_TLSDESC_LD64_LO12.
- (R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
- R_AARCH64_TLSDESC_ADD_LO12_NC.
-
-2017-03-10 Nick Clifton <nickc@redhat.com>
-
- * elf/common.h (EM_LANAI): New machine number.
- (EM_BPF): Likewise.
- (EM_WEBASSEMBLY): Likewise.
- Move low value, deprecated, numbers to their numerical
- equivalents.
-
-2017-03-08 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/21231
- * elf/common.h (GNU_PROPERTY_LOPROC): New.
- (GNU_PROPERTY_HIPROC): Likewise.
- (GNU_PROPERTY_LOUSER): Likewise.
- (GNU_PROPERTY_HIUSER): Likewise.
-
-2017-03-01 Nick Clifton <nickc@redhat.com>
-
- * elf/common.h (SHF_GNU_BUILD_NOTE): Define.
- (NT_GNU_PROPERTY_TYPE_0): Define.
- (NT_GNU_BUILD_ATTRIBUTE_OPEN): Define.
- (NT_GNU_BUILD_ATTRIBUTE_FUN): Define.
- (GNU_BUILD_ATTRIBUTE_TYPE_NUMERIC): Define.
- (GNU_BUILD_ATTRIBUTE_TYPE_STRING): Define.
- (GNU_BUILD_ATTRIBUTE_TYPE_BOOL_TRUE): Define.
- (GNU_BUILD_ATTRIBUTE_TYPE_BOOL_FALSE): Define.
- (GNU_BUILD_ATTRIBUTE_VERSION): Define.
- (GNU_BUILD_ATTRIBUTE_STACK_PROT): Define.
- (GNU_BUILD_ATTRIBUTE_RELRO): Define.
- (GNU_BUILD_ATTRIBUTE_STACK_SIZE): Define.
- (GNU_BUILD_ATTRIBUTE_TOOL): Define.
- (GNU_BUILD_ATTRIBUTE_ABI): Define.
- (GNU_BUILD_ATTRIBUTE_PIC): Define.
- (NOTE_GNU_PROPERTY_SECTION_NAME): Define.
- (GNU_BUILD_ATTRS_SECTION_NAME): Define.
- (GNU_PROPERTY_STACK_SIZE): Define.
- (GNU_PROPERTY_NO_COPY_ON_PROTECTED): Define.
- (GNU_PROPERTY_X86_ISA_1_USED): Define.
- (GNU_PROPERTY_X86_ISA_1_NEEDED): Define.
- (GNU_PROPERTY_X86_ISA_1_486): Define.
- (GNU_PROPERTY_X86_ISA_1_586): Define.
- (GNU_PROPERTY_X86_ISA_1_686): Define.
- (GNU_PROPERTY_X86_ISA_1_SSE): Define.
- (GNU_PROPERTY_X86_ISA_1_SSE2): Define.
- (GNU_PROPERTY_X86_ISA_1_SSE3): Define.
- (GNU_PROPERTY_X86_ISA_1_SSSE3): Define.
- (GNU_PROPERTY_X86_ISA_1_SSE4_1): Define.
- (GNU_PROPERTY_X86_ISA_1_SSE4_2): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX2): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX512F): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX512CD): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX512ER): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX512PF): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX512VL): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX512DQ): Define.
- (GNU_PROPERTY_X86_ISA_1_AVX512BW): Define.
+ * elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
+ (GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This.
+ (GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
+ (GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This.
+ (GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ...
+ (GNU_PROPERTY_X86_COMPAT_ISA_1_XXX): This.
+ (GNU_PROPERTY_X86_UINT32_AND_LO): New.
+ (GNU_PROPERTY_X86_UINT32_AND_HI): Likewise.
+ (GNU_PROPERTY_X86_UINT32_OR_LO): Likewise.
+ (GNU_PROPERTY_X86_UINT32_OR_HI): Likewise.
+ (GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise.
+ (GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_CMOV): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_SSE): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_SSE2): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_SSE3): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_SSSE3): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_SSE4_1): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_SSE4_2): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX2): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_FMA): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512F): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512CD): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512ER): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512PF): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512VL): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512DQ): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512BW): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512_BITALG): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512_IFMA): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512_VBMI): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2): Likewise.
+ (GNU_PROPERTY_X86_ISA_1_AVX512_VNNI): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_X86): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_X87): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_MMX): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_XMM): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_YMM): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_ZMM): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_FXSR): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_XSAVE): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_2_XSAVEC): Likewise.
+ (GNU_PROPERTY_X86_FEATURE_1_AND): Updated to
+ (GNU_PROPERTY_X86_UINT32_AND_LO + 0).
+ (GNU_PROPERTY_X86_ISA_1_NEEDED): Defined to
+ (GNU_PROPERTY_X86_UINT32_OR_LO + 0).
+ (GNU_PROPERTY_X86_FEATURE_2_NEEDED): New. Defined to
+ (GNU_PROPERTY_X86_UINT32_OR_LO + 1).
+ (GNU_PROPERTY_X86_ISA_1_USED): Defined to
+ (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 0).
+ (GNU_PROPERTY_X86_FEATURE_2_USED): New. Defined to
+ (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1).
-2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
+2018-08-24 H.J. Lu <hongjiu.lu@intel.com>
- * dis-asm.h (disasm_options_t): New typedef.
- (parse_arm_disassembler_option): Remove prototype.
- (set_arm_regname_option): Likewise.
- (get_arm_regnames): Likewise.
- (get_arm_regname_num_options): Likewise.
- (disassemble_init_s390): New prototype.
- (disassembler_options_powerpc): Likewise.
- (disassembler_options_arm): Likewise.
- (disassembler_options_s390): Likewise.
- (remove_whitespace_and_extra_commas): Likewise.
- (disassembler_options_cmp): Likewise.
- (next_disassembler_option): New inline function.
- (FOR_EACH_DISASSEMBLER_OPTION): New macro.
-
-2017-02-28 Alan Modra <amodra@gmail.com>
-
- * elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
- * elf/ppc.h (R_PPC_16DX_HA): Likewise.
-
-2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
- (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
- (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
- (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
-
-2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
- (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
-
-2017-02-22 Andrew Waterman <andrew@sifive.com>
-
- * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
- (CSR_MCOUNTEREN): Likewise.
- (scounteren): Declare register.
- (mcounteren): Likewise.
-
-2017-02-14 Andrew Waterman <andrew@sifive.com>
-
- * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
- (MASK_SFENCE_VMA): Likewise.
- (sfence_vma): Declare instruction.
-
-2017-02-14 Alan Modra <amodra@gmail.com>
-
- PR 21118
- * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
- (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
-
-2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
-
- * opcode/hppa.h: Clarify that file is part of GNU opcodes.
- * opcode/i860.h: Ditto.
- * opcode/nios2.h: Ditto.
- * opcode/nios2r1.h: Ditto.
- * opcode/nios2r2.h: Ditto.
- * opcode/pru.h: Ditto.
-
-2017-01-24 Alan Hayward <alan.hayward@arm.com>
-
- * elf/common.h (NT_ARM_SVE): Define.
-
-2017-01-04 Jiong Wang <jiong.wang@arm.com>
-
- * dwarf2.def: Sync with mainline gcc sources.
+ * elf/common.h (GNU_PROPERTY_X86_UINT32_VALID): New.
- 2017-01-04 Richard Earnshaw <rearnsha@arm.com>
- Jiong Wang <jiong.wang@arm.com>
+2018-08-21 John Darrington <john@darrington.wattle.id.au>
- * dwarf2.def (DW_OP_AARCH64_operation): Reserve the number 0xea.
- (DW_CFA_GNU_window_save): Comments the multiplexing on AArch64.
+ * elf/s12z.h: Rename R_S12Z_UKNWN_3 to R_S12Z_EXT18.
-2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
+2018-08-21 Alan Modra <amodra@gmail.com>
- * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
- (AARCH64_ARCH_V8_3): Update.
+ * opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
+ Mention use of "extract" function to provide default value.
+ (PPC_OPERAND_OPTIONAL_VALUE): Delete.
+ (ppc_optional_operand_value): Rewrite to use extract function.
-2017-01-03 Kito Cheng <kito.cheng@gmail.com>
+2018-08-18 John Darrington <john@darrington.wattle.id.au>
- * opcode/riscv-opc.h: Add support for the "q" ISA extension.
+ * opcode/s12z.h: New file.
-2017-01-03 Nick Clifton <nickc@redhat.com>
+2018-08-09 Richard Earnshaw <rearnsha@arm.com>
- * dwarf2.def: Sync with mainline gcc sources
- * dwarf2.h: Likewise.
+ * elf/arm.h: Updated comments for e_flags definitions.
- 2016-12-21 Jakub Jelinek <jakub@redhat.com>
+2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
- * dwarf2.def (DW_FORM_ref_sup): Renamed to ...
- (DW_FORM_ref_sup4): ... this. New form.
- (DW_FORM_ref_sup8): New form.
+ * elf/arc.h (Tag_ARC_ATR_version): New tag.
- 2016-10-17 Jakub Jelinek <jakub@redhat.com>
+2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
- * dwarf2.h (enum dwarf_calling_convention): Add new DWARF5
- calling convention codes.
- (enum dwarf_line_number_content_type): New.
- (enum dwarf_location_list_entry_type): Add DWARF5 DW_LLE_*
- codes.
- (enum dwarf_source_language): Add new DWARF5 DW_LANG_* codes.
- (enum dwarf_macro_record_type): Add DWARF5 DW_MACRO_* codes.
- (enum dwarf_name_index_attribute): New.
- (enum dwarf_range_list_entry): New.
- (enum dwarf_unit_type): New.
- * dwarf2.def: Add new DWARF5 DW_TAG_*, DW_FORM_*, DW_AT_*,
- DW_OP_* and DW_ATE_* entries.
+ * opcode/arc.h (ARC_OPCODE_ARCV1): Define.
- 2016-08-15 Jakub Jelinek <jakub@redhat.com>
+2018-08-01 Richard Earnshaw <rearnsha@arm.com>
- * dwarf2.def (DW_AT_string_length_bit_size,
- DW_AT_string_length_byte_size): New attributes.
+ Copy over from GCC
+ 2018-07-26 Martin Liska <mliska@suse.cz>
- 2016-08-12 Alexandre Oliva <aoliva@redhat.com>
+ PR lto/86548
+ * libiberty.h (make_temp_file_with_prefix): New function.
- PR debug/63240
- * dwarf2.def (DW_AT_deleted, DW_AT_defaulted): New.
- * dwarf2.h (enum dwarf_defaulted_attribute): New.
+2018-07-30 Jim Wilson <jimw@sifive.com>
-2017-01-02 Alan Modra <amodra@gmail.com>
+ * opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
+ (INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
+ (INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.
+
+2018-07-30 Andrew Jenner <andrew@codesourcery.com>
+
+ * elf/common.h (EM_CSKY, EM_CSKY_OLD): Define.
+ * elf/csky.h: New file.
+
+2018-07-27 Chenghua Xu <paul.hua.gm@gmail.com>
+ Maciej W. Rozycki <macro@linux-mips.org>
+
+ * elf/mips.h (AFL_ASE_MASK): Correct typo.
+
+2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
+
+ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
+
+2018-07-26 Alan Modra <amodra@gmail.com>
+
+ * elf/ppc64.h: Specify byte offset to local entry for values
+ of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return
+ value for such functions when entering via global entry point.
+ Specify meaning of a value of one in STO_PPC64_LOCAL_MASK.
+
+2018-07-24 Alan Modra <amodra@gmail.com>
+
+ PR 23430
+ * elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo.
+
+2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
+ Maciej W. Rozycki <macro@mips.com>
+
+ * elf/mips.h (AFL_ASE_MMI): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
+ * opcode/mips.h (ASE_LOONGSON_MMI): New macro.
+
+2018-07-17 Maciej W. Rozycki <macro@mips.com>
+
+ * bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member.
+
+2018-07-06 Alan Modra <amodra@gmail.com>
+
+ * diagnostics.h: Comment on macro usage.
+
+2018-07-05 Simon Marchi <simon.marchi@polymtl.ca>
+
+ * diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS):
+ Define for clang.
+
+2018-07-02 Maciej W. Rozycki <macro@mips.com>
+
+ PR tdep/8282
+ * dis-asm.h (disasm_option_arg_t): New typedef.
+ (disasm_options_and_args_t): Likewise.
+ (disasm_options_t): Add `arg' member, document members.
+ (disassembler_options_mips): New prototype.
+ (disassembler_options_arm, disassembler_options_powerpc)
+ (disassembler_options_s390): Update prototypes.
+
+2018-06-29 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/23192
+ *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
+
+2018-06-26 Alan Modra <amodra@gmail.com>
+
+ * elf/internal.h (ELF_SECTION_IN_SEGMENT): Revert last change.
+
+2018-06-24 Nick Clifton <nickc@redhat.com>
+
+ 2.31 branch created.
+
+2018-06-21 Alan Hayward <alan.hayward@arm.com>
+
+ * elf/internal.h (ELF_SECTION_IN_SEGMENT): Don’t check addresses
+ for non SHT_NOBITS.
+
+2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
+
+ Sync with GCC
+
+ 2018-05-24 Tom Rix <trix@juniper.net>
+
+ * dwarf2.def (DW_FORM_strx*, DW_FORM_addrx*): New.
+
+ 2017-11-20 Kito Cheng <kito.cheng@gmail.com>
+
+ * longlong.h [__riscv] (__umulsidi3): Define.
+ [__riscv] (umul_ppmm): Likewise.
+ [__riscv] (__muluw3): Likewise.
+
+2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
+ (AFL_ASE_MASK): Update to include AFL_ASE_GINV.
+ * opcode/mips.h: Document "+\" operand format.
+ (ASE_GINV): New macro.
+
+2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
+ Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * elf/mips.h (AFL_ASE_CRC): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_CRC.
+ * opcode/mips.h (ASE_CRC): New macro.
+ * opcode/mips.h (ASE_CRC64): Likewise.
+
+2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
+
+ * elf/xtensa.h (xtensa_read_table_entries)
+ (xtensa_compute_fill_extra_space): New declarations.
+
+2018-06-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * diagnostics.h (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): Always
+ define for GCC.
+
+2018-06-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * diagnostics.h (DIAGNOSTIC_STRINGIFY_1): New.
+ (DIAGNOSTIC_STRINGIFY): Likewise.
+ (DIAGNOSTIC_IGNORE): Replace STRINGIFY with DIAGNOSTIC_STRINGIFY.
+ (DIAGNOSTIC_IGNORE_SELF_MOVE): Define empty if not defined.
+ (DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Likewise.
+ (DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): Likewise.
+ (DIAGNOSTIC_IGNORE_SWITCH_DIFFERENT_ENUM_TYPES): Likewise.
+ (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): New.
+
+2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * diagnostics.h: Moved from ../gdb/common/diagnostics.h.
+
+2018-05-28 Bernd Edlinger <bernd.edlinger@hotmail.de>
+
+ * splay-tree.h (splay_tree_compare_strings,
+ splay_tree_delete_pointers): Declare new utility functions.
+
+2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
+
+ * opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
+
+2018-05-18 Kito Cheng <kito.cheng@gmail.com>
+
+ * elf/riscv.h (EF_RISCV_RVE): New define.
+
+2018-05-18 John Darrington <john@darrington.wattle.id.au>
+
+ * elf/s12z.h: New header.
+
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
+
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
+ (aarch64_print_operand): Support notes.
+
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
+ (aarch64_decode_insn): Accept error struct.
+
+2018-05-15 Francois H. Theron <francois.theron@netronome.com>
+
+ * opcode/nfp.h: Use uint64_t instead of bfd_vma.
+
+2018-05-10 John Darrington <john@darrington.wattle.id.au>
+
+ * elf/common.h (EM_S12Z): New macro.
+
+2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
+
+ * mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
+ Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
+ (MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
+ MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
+
+2018-05-08 Jim Wilson <jimw@sifive.com>
+
+ * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
+ (MATCH_C_SRAI64, MASK_C_SRAI64): New.
+ (MATCH_C_SLLI64, MASK_C_SLLI64): New.
+
+2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
+
+ * opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
+ (vle_num_opcodes): Likewise.
+ (spe2_num_opcodes): Likewise.
+
+2018-05-04 Alan Modra <amodra@gmail.com>
+
+ * ansidecl.h: Import from gcc.
+ * coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING
+ to s_name.
+ (struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name.
+
+2018-04-30 Francois H. Theron <francois.theron@netronome.com>
+
+ * dis-asm.h: Added print_nfp_disassembler_options prototype.
+ * elf/common.h: Added EM_NFP, officially assigned. See Google Group
+ Generic System V Application Binary Interface.
+ * elf/nfp.h: New, for NFP support.
+ * opcode/nfp.h: New, for NFP support.
+
+2018-04-25 Christophe Lyon <christophe.lyon@st.com>
+ Mickaël Guêné <mickael.guene@st.com>
+
+ * elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
+ R_ARM_TLS_IE32_FDPIC.
+
+2018-04-25 Christophe Lyon <christophe.lyon@st.com>
+ Mickaël Guêné <mickael.guene@st.com>
+
+ * elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
+ (R_ARM_FUNCDESC)
+ (R_ARM_FUNCDESC_VALUE): Define new relocations.
+
+2018-04-25 Christophe Lyon <christophe.lyon@st.com>
+ Mickaël Guêné <mickael.guene@st.com>
+
+ * elf/arm.h (EF_ARM_FDPIC): New.
+
+2018-04-18 Alan Modra <amodra@gmail.com>
+
+ * coff/mipspe.h: Delete.
+
+2018-04-18 Alan Modra <amodra@gmail.com>
+
+ * aout/dynix3.h: Delete.
+
+2018-04-17 Andrew Sadek <andrew.sadek.se@gmail.com>
+
+ Microblaze Target: PIC data text relative
+
+ * bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct.
+ * elf/microblaze.h (Add 3 new relocations):
+ R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64
+ and R_MICROBLAZE_TEXTREL_32_LO for relax function.
+
+2018-04-17 Alan Modra <amodra@gmail.com>
+
+ * elf/i370.h: Revert removal.
+ * elf/i860.h: Likewise.
+ * elf/i960.h: Likewise.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * coff/sparc.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * aout/host.h: Remove m68k-aout and m68k-coff support.
+ * aout/hp300hpux.h: Delete.
+ * coff/apollo.h: Delete.
+ * coff/aux-coff.h: Delete.
+ * coff/m68k.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * dis-asm.h: Remove sh5 and sh64 support.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * coff/internal.h: Remove w65 support.
+ * coff/w65.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * coff/we32k.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * coff/internal.h: Remove m88k support.
+ * coff/m88k.h: Delete.
+ * opcode/m88k.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * elf/i370.h: Delete.
+ * opcode/i370.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * coff/h8500.h: Delete.
+ * coff/internal.h: Remove h8500 support.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * coff/h8300.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * ieee.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * aout/host.h: Remove newsos3 support.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * nlm/ChangeLog-9315: Delete.
+ * nlm/alpha-ext.h: Delete.
+ * nlm/common.h: Delete.
+ * nlm/external.h: Delete.
+ * nlm/i386-ext.h: Delete.
+ * nlm/internal.h: Delete.
+ * nlm/ppc-ext.h: Delete.
+ * nlm/sparc32-ext.h: Delete.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * opcode/tahoe.h: Delete.
+
+2018-04-11 Alan Modra <amodra@gmail.com>
+
+ * aout/adobe.h: Delete.
+ * aout/reloc.h: Delete.
+ * coff/i860.h: Delete.
+ * coff/i960.h: Delete.
+ * elf/i860.h: Delete.
+ * elf/i960.h: Delete.
+ * opcode/i860.h: Delete.
+ * opcode/i960.h: Delete.
+ * aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
+ * aout/ar.h (ARMAGB): Remove.
+ * coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
+ union internal_auxent): Remove i960 support.
+
+2018-04-09 Alan Modra <amodra@gmail.com>
+
+ * elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
+ * elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
+
+2018-03-28 Renlin Li <renlin.li@arm.com>
+
+ PR ld/22970
+ * elf/aarch64.h: Add relocation number for
+ R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12,
+ R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC,
+ R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12,
+ R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC,
+ R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12,
+ R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC,
+ R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12,
+ R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC.
+
+2018-03-28 Nick Clifton <nickc@redhat.com>
+
+ PR 22988
+ * opcode/aarch64.h (enum aarch64_opnd): Add
+ AARCH64_OPND_SVE_ADDR_R.
+
+2018-03-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * elf/common.h (DF_1_KMOD): New.
+ (DF_1_WEAKFILTER): Likewise.
+ (DF_1_NOCOMMON): Likewise.
+
+2018-03-14 Kito Cheng <kito.cheng@gmail.com>
+
+ * opcode/riscv.h (OP_MASK_FUNCT3): New.
+ (OP_SH_FUNCT3): Likewise.
+ (OP_MASK_FUNCT7): Likewise.
+ (OP_SH_FUNCT7): Likewise.
+ (OP_MASK_OP2): Likewise.
+ (OP_SH_OP2): Likewise.
+ (OP_MASK_CFUNCT4): Likewise.
+ (OP_SH_CFUNCT4): Likewise.
+ (OP_MASK_CFUNCT3): Likewise.
+ (OP_SH_CFUNCT3): Likewise.
+ (riscv_insn_types): Likewise.
+
+2018-03-13 Nick Clifton <nickc@redhat.com>
+
+ PR 22113
+ * coff/pe.h (struct pex64_unwind_info): Add a rawUnwindCodesEnd
+ field.
+
+2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * opcode/i386 (OLDGCC_COMPAT): Removed.
+
+2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
+
+2018-02-20 Maciej W. Rozycki <macro@mips.com>
+
+ * opcode/mips.h: Remove `M' operand code.
+
+2018-02-12 Zebediah Figura <z.figura12@gmail.com>
+
+ * coff/msdos.h: New header.
+ * coff/pe.h: Move common defines to msdos.h.
+ * coff/powerpc.h: Likewise.
+
+2018-01-13 Nick Clifton <nickc@redhat.com>
+
+ 2.30 branch created.
+
+2018-01-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR ld/22393
+ * bfdlink.h (bfd_link_info): Add separate_code.
+
+2018-01-04 Jim Wilson <jimw@sifive.com>
+
+ * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename
+ DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL.
+ (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry.
+ Add alias to map mbadaddr to CSR_MTVAL.
+
+2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
-For older changes see ChangeLog-2016
+For older changes see ChangeLog-2017
\f
-Copyright (C) 2017 Free Software Foundation, Inc.
+Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff